// Verilog netlist produced by program LSE :  version Diamond (64-bit) 3.13.0.56.2
// Netlist written on Sun Jun 23 13:11:47 2024
//
// Verilog Description of module DDS
//

module DDS (clk, rst, key, seg, led, P, seg_dig) /* synthesis syn_module_defined=1 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(3[8:11])
    input clk;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(4[9:12])
    input rst /* synthesis syn_force_pads=1 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(5[9:12])
    input key /* synthesis syn_force_pads=1 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(6[9:12])
    output [15:0]seg;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(7[20:23])
    output [7:0]led;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(8[19:22])
    output [11:0]P;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(9[20:21])
    output [1:0]seg_dig;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(10[20:27])
    
    wire clk_c /* synthesis is_clock=1 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(4[9:12])
    wire rst_c /* synthesis syn_force_pads=1 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(5[9:12])
    wire key_c /* synthesis syn_force_pads=1 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(6[9:12])
    wire clk_pll /* synthesis is_clock=1, SET_AS_NETWORK=clk_pll */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(40[6:13])
    wire R_11__N_429 /* synthesis is_clock=1, SET_AS_NETWORK=\ALU_M/R_11__N_429 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(5[20:21])
    
    wire GND_net, VCC_net, n1241, n1240, n1239, n1238, n1237, 
        n3213, n3073, n3072, led_c_7, led_c_6, led_c_5, led_c_4, 
        led_c_3, led_c_2, led_c_1, led_c_0, P_c_11, P_c_10, P_c_9, 
        P_c_8, P_c_7, P_c_6, P_c_5, P_c_4, P_c_3, P_c_2, P_c_1, 
        P_c_0;
    wire [11:0]A;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(16[12:13])
    wire [11:0]B;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(17[12:13])
    wire [11:0]C;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(18[12:13])
    wire [11:0]D;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(19[12:13])
    wire [11:0]SP;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(20[12:14])
    
    wire flag, IRQ_EN;
    wire [9:0]PC;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(23[25:27])
    wire [11:0]PC_temp;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(24[12:19])
    wire [11:0]prog;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(29[12:16])
    
    wire clk_pll_enable_66;
    wire [11:0]ram_in;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(31[12:18])
    wire [11:0]ram_out;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(32[13:20])
    
    wire ram_we;
    wire [11:0]alu_a;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(34[12:17])
    wire [11:0]alu_b;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(35[12:17])
    
    wire alu_cin;
    wire [11:0]alu_c;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(37[13:18])
    wire [3:0]alu_type;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(38[11:19])
    
    wire alu_co, n3070, n3071;
    wire [9:0]PC_9__N_179;
    
    wire n1203, n226, n227, n228, n229, n230, n231, n232, n233, 
        n234, n235, n3207, n7796, n7693, n7649, n3807, n3809, 
        n3811, n3815, n3817;
    wire [9:0]PC_9__N_169;
    
    wire n6631, n7145, clk_pll_enable_110, n1244, n3212, n468, n469, 
        clk_pll_enable_12;
    wire [9:0]PC_9__N_159;
    wire [11:0]A_11__N_225;
    
    wire n1854, n3409, n2297, n2296, n2295, n18, n17, n1, n7433, 
        n2294, n2293, n2292, n2291, n2290, n2289, n2288, n7797, 
        n7795, clk_pll_enable_33, n7794, n4, n11, n3208, n1177, 
        n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, 
        n1186, n1187, n7721, clk_pll_enable_55, n7720, n7793, n3246, 
        Co_N_435, n1242, n3211, n1251, n3210, n3209, n7791, n2287, 
        n2286, n1605, n1606, n1607, n1604, n1603, n1602, n1601, 
        n1600, n1599, n1598, n1608, n1609, n1611, n1612, n1613, 
        n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621, 
        n1622, n1623, n7148, clk_pll_enable_143, n2558, n2557, n2556, 
        n2555, n2554, clk_pll_enable_77, n2552, n7748, n7745, n7742, 
        n2546, n2545, n2544, n2543, n2542, n2540, n2539, n2538, 
        n2537, n2310, n2309, n2308, n2307, n2306, n2305, n2304, 
        n2302, n2301, n2300, n2314, n2315, n2316, n2317, n2318, 
        n2319, n2320, n2321, n2322, n2323, n2324, n2325, n2523, 
        n2522, n2521, n2520, n2519, n2518, n2516, n6, n7701, 
        n7719, n7733, n4283, n7736, n7703, n7702, n2493, n2492, 
        n2491, n2490, n2489, n2488, n2487, n14, n3745, n3747, 
        n3749, n3751, n3079, n3078, n7475, n3170, n2439, n2438, 
        n2437, n2436, n2435, n2434, n2433, n2432, n2431, n3351, 
        n7704, clk_pll_enable_145, n3759, n3757, n3755, n3753, n2361, 
        n3801, n3803, n3805, n14_adj_436, n7717, n7425, n7424, 
        n31, n12, n4534, n7716, n3076, n7715, n6626, n3075, 
        n7790, n3074, n2, n17_adj_437, n18_adj_438, n16, n12_adj_439, 
        n7071, n7196, n15, n17_adj_440, n30, n6630, n6641, n15_adj_441, 
        n17_adj_442, n30_adj_443, n29, n25, n7123, n7013, n6640, 
        clk_pll_enable_99, n4273, n7734, n7753, clk_pll_enable_2, 
        n7713, clk_pll_enable_119, n7712, n7705, n7752, n7751, n5295, 
        n7749, n6639, n7529, n6638, n8, n7, n7264, n4_adj_444, 
        n7528, n7_adj_445, n7527, clk_pll_enable_130, n5236, n7665, 
        n17_adj_446, n18_adj_447, n4557, n4_adj_448, n7711, n5277, 
        clk_pll_enable_11, n7663, n4556, n17_adj_449, n18_adj_450, 
        clk_pll_enable_139, n7674, clk_pll_enable_14, n6637, n17_adj_451, 
        n18_adj_452, n7710, n7_adj_453, n5264, n5266, n3832, n7747, 
        n7458, n7664, n7457, n3818, n3816, n3814, n3812, n3810, 
        n3808, n3806, n3804, n3802, n3800, n3799, n7456, n7739, 
        n3760, n3758, n3756, n3754, n3752, n3750, n3748, n3746, 
        n3744, n3743, n7746, n7708, n7706, clk_pll_enable_44, clk_pll_enable_88, 
        n6635, n7744, n6634, n7222, n7743, n7675, n4568, n4518, 
        n7692, n5232, n7741, n6629, n6628, n7985, n3, n7415, 
        n7728, n6751, n5227, n7727, n3_adj_454, n6627, n7740, 
        clk_pll_enable_144, n7210, n6633, n5439, n4_adj_455, n7726, 
        n7208, n7738, n7725, n15_adj_456, n6632, clk_pll_enable_147, 
        n30_adj_457, clk_pll_enable_146, clk_pll_enable_116, n3420, 
        n7737, n7724, n3410, n7434, n7414, n17_adj_458, n18_adj_459, 
        n7986, clk_pll_enable_148;
    
    VHI i2 (.Z(VCC_net));
    LUT4 i5343_2_lut_3_lut (.A(n1239), .B(rst_c), .C(n7753), .Z(clk_pll_enable_130)) /* synthesis lut_function=(A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i5343_2_lut_3_lut.init = 16'h8080;
    LUT4 i3162_3_lut_4_lut (.A(n7715), .B(n7706), .C(C[8]), .D(B[8]), 
         .Z(n5264)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam i3162_3_lut_4_lut.init = 16'hf780;
    LUT4 i3380_2_lut_4_lut (.A(PC_9__N_179[7]), .B(ram_out[7]), .C(alu_co), 
         .D(prog[2]), .Z(n2489)) /* synthesis lut_function=(A (B (D)+!B !(C+!(D)))+!A (B (C (D)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(284[7:23])
    defparam i3380_2_lut_4_lut.init = 16'hca00;
    FD1P3AY led_i0_i1 (.D(A[0]), .SP(clk_pll_enable_33), .CK(clk_pll), 
            .Q(led_c_0));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam led_i0_i1.GSR = "ENABLED";
    LUT4 i1_2_lut_3_lut_4_lut (.A(n1239), .B(rst_c), .C(prog[2]), .D(prog[3]), 
         .Z(n4_adj_448)) /* synthesis lut_function=(((C (D))+!B)+!A) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i1_2_lut_3_lut_4_lut.init = 16'hf777;
    OB P_pad_5 (.I(P_c_5), .O(P[5]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(9[20:21])
    OB P_pad_6 (.I(P_c_6), .O(P[6]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(9[20:21])
    LUT4 i255_2_lut (.A(n1238), .B(n1237), .Z(n1623)) /* synthesis lut_function=(A+(B)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i255_2_lut.init = 16'heeee;
    LUT4 mux_71_i4_3_lut_rep_46 (.A(PC_9__N_179[3]), .B(ram_out[3]), .C(alu_co), 
         .Z(n7704)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(284[7:23])
    defparam mux_71_i4_3_lut_rep_46.init = 16'hcaca;
    LUT4 mux_649_i10_3_lut_4_lut (.A(n7715), .B(n7706), .C(C[9]), .D(B[9]), 
         .Z(n2302)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam mux_649_i10_3_lut_4_lut.init = 16'hf780;
    FD1P3AX ram_we_142 (.D(n4518), .SP(clk_pll_enable_2), .CK(clk_pll), 
            .Q(ram_we));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam ram_we_142.GSR = "ENABLED";
    ram RAM_M (.clk_pll(clk_pll), .VCC_net(VCC_net), .GND_net(GND_net), 
        .ram_we(ram_we), .PC({PC}), .ram_in({ram_in}), .ram_out({ram_out})) /* synthesis NGD_DRC_MASK=1, syn_module_defined=1 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(47[5] 55[2])
    LUT4 mux_651_i11_3_lut_4_lut (.A(n7713), .B(n7706), .C(D[10]), .D(n2301), 
         .Z(n2315)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;
    defparam mux_651_i11_3_lut_4_lut.init = 16'hf780;
    LUT4 i3377_2_lut_4_lut (.A(PC_9__N_179[3]), .B(ram_out[3]), .C(alu_co), 
         .D(prog[2]), .Z(n2493)) /* synthesis lut_function=(A (B (D)+!B !(C+!(D)))+!A (B (C (D)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(284[7:23])
    defparam i3377_2_lut_4_lut.init = 16'hca00;
    OB P_pad_7 (.I(P_c_7), .O(P[7]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(9[20:21])
    OB P_pad_8 (.I(P_c_8), .O(P[8]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(9[20:21])
    OB P_pad_9 (.I(P_c_9), .O(P[9]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(9[20:21])
    OB P_pad_10 (.I(P_c_10), .O(P[10]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(9[20:21])
    OB P_pad_11 (.I(P_c_11), .O(P[11]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(9[20:21])
    OB led_pad_0 (.I(led_c_0), .O(led[0]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(8[19:22])
    OB led_pad_1 (.I(led_c_1), .O(led[1]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(8[19:22])
    OB led_pad_2 (.I(led_c_2), .O(led[2]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(8[19:22])
    FD1P3AX A_i0_i0 (.D(A_11__N_225[0]), .SP(clk_pll_enable_44), .CK(clk_pll), 
            .Q(A[0]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam A_i0_i0.GSR = "DISABLED";
    FD1P3AX B_i0_i0 (.D(alu_c[0]), .SP(clk_pll_enable_55), .CK(clk_pll), 
            .Q(B[0]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam B_i0_i0.GSR = "DISABLED";
    FD1P3AX C_i0_i0 (.D(alu_c[0]), .SP(clk_pll_enable_66), .CK(clk_pll), 
            .Q(C[0]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam C_i0_i0.GSR = "DISABLED";
    FD1P3AX D_i0_i0 (.D(alu_c[0]), .SP(clk_pll_enable_77), .CK(clk_pll), 
            .Q(D[0]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam D_i0_i0.GSR = "DISABLED";
    FD1P3AX alu_b_i0_i0 (.D(n2325), .SP(clk_pll_enable_88), .CK(clk_pll), 
            .Q(alu_b[0]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam alu_b_i0_i0.GSR = "DISABLED";
    FD1P3AX ram_in_i0_i0 (.D(A[0]), .SP(clk_pll_enable_99), .CK(clk_pll), 
            .Q(ram_in[0]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam ram_in_i0_i0.GSR = "DISABLED";
    FD1P3AX P_i0_i1 (.D(A[0]), .SP(clk_pll_enable_110), .CK(clk_pll), 
            .Q(P_c_0));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam P_i0_i1.GSR = "DISABLED";
    LUT4 i3353_4_lut (.A(alu_c[1]), .B(n5236), .C(ram_out[1]), .D(n3170), 
         .Z(n1621)) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i3353_4_lut.init = 16'hc088;
    FD1P3AX PC_i0_i0 (.D(n3410), .SP(clk_pll_enable_116), .CK(clk_pll), 
            .Q(PC[0]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam PC_i0_i0.GSR = "ENABLED";
    ALU ALU_M (.alu_a({alu_a}), .alu_type({alu_type}), .alu_b({alu_b}), 
        .alu_c({alu_c}), .R_11__N_429(R_11__N_429), .GND_net(GND_net), 
        .alu_co(alu_co), .Co_N_435(Co_N_435), .n7724(n7724), .alu_cin(alu_cin)) /* synthesis syn_module_defined=1 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(57[5] 64[2])
    FD1P3AX alu_cin_153 (.D(n4534), .SP(clk_pll_enable_11), .CK(clk_pll), 
            .Q(alu_cin));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam alu_cin_153.GSR = "DISABLED";
    LUT4 i3337_2_lut (.A(ram_out[1]), .B(n1239), .Z(n1608)) /* synthesis lut_function=(A (B)) */ ;
    defparam i3337_2_lut.init = 16'h8888;
    FD1S3JX statu_FSM_i1 (.D(n1244), .CK(clk_pll), .PD(n1237), .Q(n1242));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam statu_FSM_i1.GSR = "ENABLED";
    PLL pll_m (.clk_c(clk_c), .clk_pll(clk_pll), .GND_net(GND_net)) /* synthesis NGD_DRC_MASK=1, syn_module_defined=1 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(42[5] 45[2])
    VLO i1 (.Z(GND_net));
    LUT4 mux_726_i5_3_lut_4_lut (.A(n7716), .B(prog[4]), .C(PC_temp[4]), 
         .D(n3208), .Z(n2542)) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;
    defparam mux_726_i5_3_lut_4_lut.init = 16'hf1e0;
    LUT4 i3354_4_lut (.A(alu_c[2]), .B(n5236), .C(ram_out[2]), .D(n3170), 
         .Z(n1620)) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i3354_4_lut.init = 16'hc088;
    LUT4 mux_649_i11_3_lut_4_lut (.A(n7715), .B(n7706), .C(C[10]), .D(B[10]), 
         .Z(n2301)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam mux_649_i11_3_lut_4_lut.init = 16'hf780;
    LUT4 i3324_2_lut (.A(ram_out[2]), .B(n1239), .Z(n1607)) /* synthesis lut_function=(A (B)) */ ;
    defparam i3324_2_lut.init = 16'h8888;
    LUT4 i2_4_lut (.A(prog[4]), .B(prog[1]), .C(prog[2]), .D(prog[3]), 
         .Z(n2523)) /* synthesis lut_function=(!(A+!(B (C (D)+!C !(D))))) */ ;
    defparam i2_4_lut.init = 16'h4004;
    LUT4 mux_726_i7_3_lut_4_lut (.A(n7716), .B(prog[4]), .C(PC_temp[6]), 
         .D(n3210), .Z(n2540)) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;
    defparam mux_726_i7_3_lut_4_lut.init = 16'hf1e0;
    LUT4 i3195_3_lut_4_lut (.A(n7716), .B(prog[4]), .C(PC_temp[5]), .D(n3209), 
         .Z(n5295)) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;
    defparam i3195_3_lut_4_lut.init = 16'hf1e0;
    LUT4 i3355_4_lut (.A(alu_c[3]), .B(n5236), .C(ram_out[3]), .D(n3170), 
         .Z(n1619)) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i3355_4_lut.init = 16'hc088;
    LUT4 mux_647_i11_3_lut (.A(D[10]), .B(A[10]), .C(n11), .Z(n2287)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam mux_647_i11_3_lut.init = 16'hcaca;
    FD1P3AX flag_150 (.D(alu_co), .SP(clk_pll_enable_12), .CK(clk_pll), 
            .Q(flag));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam flag_150.GSR = "DISABLED";
    PUR PUR_INST (.PUR(VCC_net));
    defparam PUR_INST.RST_PULSE = 1;
    OB led_pad_3 (.I(led_c_3), .O(led[3]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(8[19:22])
    FD1P3AX alu_a_i0_i0 (.D(n2297), .SP(clk_pll_enable_130), .CK(clk_pll), 
            .Q(alu_a[0]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam alu_a_i0_i0.GSR = "DISABLED";
    OB led_pad_4 (.I(led_c_4), .O(led[4]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(8[19:22])
    OB led_pad_5 (.I(led_c_5), .O(led[5]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(8[19:22])
    OB led_pad_6 (.I(led_c_6), .O(led[6]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(8[19:22])
    OB led_pad_7 (.I(led_c_7), .O(led[7]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(8[19:22])
    OB seg_pad_0 (.I(GND_net), .O(seg[0]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(7[20:23])
    LUT4 mux_32_Mux_7_i17_3_lut (.A(SP[7]), .B(n228), .C(prog[0]), .Z(n17_adj_440)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(100[5] 230[13])
    defparam mux_32_Mux_7_i17_3_lut.init = 16'hcaca;
    OB seg_pad_1 (.I(GND_net), .O(seg[1]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(7[20:23])
    OB seg_pad_2 (.I(GND_net), .O(seg[2]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(7[20:23])
    OB seg_pad_3 (.I(GND_net), .O(seg[3]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(7[20:23])
    OB seg_pad_4 (.I(GND_net), .O(seg[4]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(7[20:23])
    OB seg_pad_5 (.I(GND_net), .O(seg[5]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(7[20:23])
    OB seg_pad_6 (.I(GND_net), .O(seg[6]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(7[20:23])
    OB seg_pad_7 (.I(GND_net), .O(seg[7]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(7[20:23])
    OB seg_pad_8 (.I(GND_net), .O(seg[8]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(7[20:23])
    OB seg_pad_9 (.I(GND_net), .O(seg[9]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(7[20:23])
    OB seg_pad_10 (.I(GND_net), .O(seg[10]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(7[20:23])
    OB seg_pad_11 (.I(GND_net), .O(seg[11]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(7[20:23])
    OB seg_pad_12 (.I(GND_net), .O(seg[12]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(7[20:23])
    OB seg_pad_13 (.I(GND_net), .O(seg[13]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(7[20:23])
    OB seg_pad_14 (.I(GND_net), .O(seg[14]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(7[20:23])
    LUT4 i3411_2_lut (.A(ram_out[3]), .B(n1239), .Z(n1606)) /* synthesis lut_function=(A (B)) */ ;
    defparam i3411_2_lut.init = 16'h8888;
    LUT4 i5326_4_lut (.A(prog[4]), .B(n7208), .C(n7210), .D(n7713), 
         .Z(clk_pll_enable_144)) /* synthesis lut_function=(!(A (((D)+!C)+!B)+!A !(B (C)))) */ ;
    defparam i5326_4_lut.init = 16'h40c0;
    LUT4 mux_647_i12_3_lut (.A(D[11]), .B(A[11]), .C(n11), .Z(n2286)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam mux_647_i12_3_lut.init = 16'hcaca;
    CCU2D add_179_11 (.A0(PC[9]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n6630), 
          .S0(PC_9__N_179[9]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(184[18:27])
    defparam add_179_11.INIT0 = 16'h5aaa;
    defparam add_179_11.INIT1 = 16'h0000;
    defparam add_179_11.INJECT1_0 = "NO";
    defparam add_179_11.INJECT1_1 = "NO";
    LUT4 mux_1194_i2_4_lut (.A(PC[1]), .B(PC_9__N_179[1]), .C(n2361), 
         .D(n1244), .Z(n3078)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam mux_1194_i2_4_lut.init = 16'hcac0;
    FD1P3AX IRQ_EN_143 (.D(n3351), .SP(clk_pll_enable_14), .CK(clk_pll), 
            .Q(IRQ_EN));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam IRQ_EN_143.GSR = "ENABLED";
    TSALL TSALL_INST (.TSALL(GND_net));
    PFUMX i5431 (.BLUT(n7528), .ALUT(n7527), .C0(prog[3]), .Z(n7529));
    PFUMX mux_1135_i5 (.BLUT(n2492), .ALUT(n2436), .C0(n7727), .Z(n3208));
    FD1P3AX PC_temp__0__i1 (.D(n3079), .SP(clk_pll_enable_139), .CK(clk_pll), 
            .Q(PC_temp[0]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam PC_temp__0__i1.GSR = "DISABLED";
    LUT4 prog_2__bdd_4_lut_5392 (.A(prog[2]), .B(prog[0]), .C(prog[3]), 
         .D(prog[1]), .Z(n5439)) /* synthesis lut_function=(A (C (D))+!A !(B+(C+(D)))) */ ;
    defparam prog_2__bdd_4_lut_5392.init = 16'ha001;
    LUT4 i3356_4_lut (.A(alu_c[4]), .B(n5236), .C(ram_out[4]), .D(n3170), 
         .Z(n1618)) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i3356_4_lut.init = 16'hc088;
    LUT4 mux_728_i1_3_lut (.A(n2522), .B(PC_9__N_179[0]), .C(n7222), .Z(n2558)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(275[5] 292[12])
    defparam mux_728_i1_3_lut.init = 16'hcaca;
    CCU2D add_178_11 (.A0(SP[9]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(SP[10]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n6641), 
          .S0(n1178), .S1(n1177));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(181[13:19])
    defparam add_178_11.INIT0 = 16'h5aaa;
    defparam add_178_11.INIT1 = 16'h5aaa;
    defparam add_178_11.INJECT1_0 = "NO";
    defparam add_178_11.INJECT1_1 = "NO";
    PFUMX mux_1135_i4 (.BLUT(n2493), .ALUT(n2437), .C0(n7727), .Z(n3207));
    LUT4 mux_726_i9_3_lut_4_lut (.A(n7716), .B(prog[4]), .C(PC_temp[8]), 
         .D(n3212), .Z(n2538)) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;
    defparam mux_726_i9_3_lut_4_lut.init = 16'hf1e0;
    LUT4 i3408_2_lut (.A(ram_out[4]), .B(n1239), .Z(n1605)) /* synthesis lut_function=(A (B)) */ ;
    defparam i3408_2_lut.init = 16'h8888;
    CCU2D add_178_9 (.A0(SP[7]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(SP[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n6640), 
          .COUT(n6641), .S0(n1180), .S1(n1179));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(181[13:19])
    defparam add_178_9.INIT0 = 16'h5aaa;
    defparam add_178_9.INIT1 = 16'h5aaa;
    defparam add_178_9.INJECT1_0 = "NO";
    defparam add_178_9.INJECT1_1 = "NO";
    FD1P3AX prog__1__i1 (.D(ram_out[0]), .SP(clk_pll_enable_143), .CK(clk_pll), 
            .Q(prog[0]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam prog__1__i1.GSR = "DISABLED";
    LUT4 mux_726_i10_3_lut_4_lut (.A(n7716), .B(prog[4]), .C(PC_temp[9]), 
         .D(n3213), .Z(n2537)) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;
    defparam mux_726_i10_3_lut_4_lut.init = 16'hf1e0;
    CCU2D add_179_9 (.A0(PC[7]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(PC[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n6629), 
          .COUT(n6630), .S0(PC_9__N_179[7]), .S1(PC_9__N_179[8]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(184[18:27])
    defparam add_179_9.INIT0 = 16'h5aaa;
    defparam add_179_9.INIT1 = 16'h5aaa;
    defparam add_179_9.INJECT1_0 = "NO";
    defparam add_179_9.INJECT1_1 = "NO";
    LUT4 prog_1__bdd_4_lut_5528_4_lut_4_lut (.A(prog[3]), .B(prog[2]), .C(prog[0]), 
         .D(prog[1]), .Z(n7664)) /* synthesis lut_function=(!(A+(B (C+(D))+!B !(D)))) */ ;
    defparam prog_1__bdd_4_lut_5528_4_lut_4_lut.init = 16'h1104;
    LUT4 i5244_3_lut_4_lut_4_lut (.A(n1239), .B(n18_adj_452), .C(n1241), 
         .D(PC_9__N_179[1]), .Z(PC_9__N_169[1])) /* synthesis lut_function=(A (B)+!A (C (D))) */ ;
    defparam i5244_3_lut_4_lut_4_lut.init = 16'hd888;
    LUT4 i5255_3_lut_4_lut_4_lut (.A(n1239), .B(n18_adj_459), .C(n1241), 
         .D(PC_9__N_179[4]), .Z(PC_9__N_169[4])) /* synthesis lut_function=(A (B)+!A (C (D))) */ ;
    defparam i5255_3_lut_4_lut_4_lut.init = 16'hd888;
    IB key_pad (.I(key), .O(key_c));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(6[9:12])
    FD1P3AX SP_i0_i1 (.D(n3800), .SP(clk_pll_enable_146), .CK(clk_pll), 
            .Q(SP[1]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam SP_i0_i1.GSR = "ENABLED";
    LUT4 i5267_3_lut_4_lut_4_lut (.A(n1239), .B(n18_adj_438), .C(PC_9__N_179[5]), 
         .D(n1241), .Z(PC_9__N_169[5])) /* synthesis lut_function=(A (B)+!A (C (D))) */ ;
    defparam i5267_3_lut_4_lut_4_lut.init = 16'hd888;
    LUT4 i3309_2_lut (.A(flag), .B(prog[3]), .Z(n4534)) /* synthesis lut_function=(A (B)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(100[5] 230[13])
    defparam i3309_2_lut.init = 16'h8888;
    PFUMX i5540 (.BLUT(n7736), .ALUT(n7737), .C0(prog[0]), .Z(n7738));
    CCU2D add_178_7 (.A0(SP[5]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(SP[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n6639), 
          .COUT(n6640), .S0(n1182), .S1(n1181));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(181[13:19])
    defparam add_178_7.INIT0 = 16'h5aaa;
    defparam add_178_7.INIT1 = 16'h5aaa;
    defparam add_178_7.INJECT1_0 = "NO";
    defparam add_178_7.INJECT1_1 = "NO";
    IB rst_pad (.I(rst), .O(rst_c));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(5[9:12])
    IB clk_pad (.I(clk), .O(clk_c));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(4[9:12])
    OB seg_dig_pad_0 (.I(GND_net), .O(seg_dig[0]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(10[20:27])
    OB seg_dig_pad_1 (.I(GND_net), .O(seg_dig[1]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(10[20:27])
    OB P_pad_0 (.I(P_c_0), .O(P[0]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(9[20:21])
    OB P_pad_1 (.I(P_c_1), .O(P[1]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(9[20:21])
    OB P_pad_2 (.I(P_c_2), .O(P[2]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(9[20:21])
    OB P_pad_3 (.I(P_c_3), .O(P[3]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(9[20:21])
    OB P_pad_4 (.I(P_c_4), .O(P[4]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(9[20:21])
    LUT4 i3369_2_lut_2_lut (.A(prog[4]), .B(alu_c[5]), .Z(n2435)) /* synthesis lut_function=(!(A+!(B))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i3369_2_lut_2_lut.init = 16'h4444;
    OB seg_pad_15 (.I(GND_net), .O(seg[15]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(7[20:23])
    CCU2D add_178_5 (.A0(SP[3]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(SP[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n6638), 
          .COUT(n6639), .S0(n1184), .S1(n1183));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(181[13:19])
    defparam add_178_5.INIT0 = 16'h5aaa;
    defparam add_178_5.INIT1 = 16'h5aaa;
    defparam add_178_5.INJECT1_0 = "NO";
    defparam add_178_5.INJECT1_1 = "NO";
    PFUMX mux_730_i1 (.BLUT(n2546), .ALUT(n2558), .C0(n7703), .Z(PC_9__N_159[0]));
    LUT4 mux_649_i12_3_lut_4_lut (.A(n7715), .B(n7706), .C(C[11]), .D(B[11]), 
         .Z(n2300)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam mux_649_i12_3_lut_4_lut.init = 16'hf780;
    LUT4 i5242_3_lut_4_lut_4_lut (.A(n1239), .B(n18_adj_450), .C(PC_9__N_179[2]), 
         .D(n1241), .Z(PC_9__N_169[2])) /* synthesis lut_function=(A (B)+!A (C (D))) */ ;
    defparam i5242_3_lut_4_lut_4_lut.init = 16'hd888;
    LUT4 i3357_4_lut (.A(alu_c[5]), .B(n5236), .C(ram_out[5]), .D(n3170), 
         .Z(n1617)) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i3357_4_lut.init = 16'hc088;
    LUT4 mux_651_i4_3_lut_4_lut (.A(n7713), .B(n7706), .C(D[3]), .D(n2308), 
         .Z(n2322)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;
    defparam mux_651_i4_3_lut_4_lut.init = 16'hf780;
    FD1P3AX SP_i0_i2 (.D(n3802), .SP(clk_pll_enable_146), .CK(clk_pll), 
            .Q(SP[2]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam SP_i0_i2.GSR = "ENABLED";
    FD1P3AX SP_i0_i3 (.D(n3804), .SP(clk_pll_enable_146), .CK(clk_pll), 
            .Q(SP[3]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam SP_i0_i3.GSR = "ENABLED";
    FD1P3AX SP_i0_i4 (.D(n3806), .SP(clk_pll_enable_146), .CK(clk_pll), 
            .Q(SP[4]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam SP_i0_i4.GSR = "ENABLED";
    FD1P3AX SP_i0_i5 (.D(n3808), .SP(clk_pll_enable_146), .CK(clk_pll), 
            .Q(SP[5]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam SP_i0_i5.GSR = "ENABLED";
    FD1P3AX SP_i0_i6 (.D(n3810), .SP(clk_pll_enable_146), .CK(clk_pll), 
            .Q(SP[6]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam SP_i0_i6.GSR = "ENABLED";
    FD1P3AX SP_i0_i7 (.D(n3812), .SP(clk_pll_enable_146), .CK(clk_pll), 
            .Q(SP[7]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam SP_i0_i7.GSR = "ENABLED";
    FD1P3AY SP_i0_i8 (.D(n3814), .SP(clk_pll_enable_146), .CK(clk_pll), 
            .Q(SP[8]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam SP_i0_i8.GSR = "ENABLED";
    FD1P3AY SP_i0_i9 (.D(n3816), .SP(clk_pll_enable_146), .CK(clk_pll), 
            .Q(SP[9]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam SP_i0_i9.GSR = "ENABLED";
    FD1P3AX SP_i0_i10 (.D(n3818), .SP(clk_pll_enable_146), .CK(clk_pll), 
            .Q(SP[10]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam SP_i0_i10.GSR = "ENABLED";
    FD1P3AY led_i0_i2 (.D(A[1]), .SP(clk_pll_enable_33), .CK(clk_pll), 
            .Q(led_c_1));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam led_i0_i2.GSR = "ENABLED";
    LUT4 i5352_3_lut_then_4_lut (.A(prog[4]), .B(prog[0]), .C(prog[2]), 
         .D(prog[1]), .Z(n7791)) /* synthesis lut_function=(A ((C+!(D))+!B)+!A !(C (D))) */ ;
    defparam i5352_3_lut_then_4_lut.init = 16'ha7ff;
    LUT4 i5333_2_lut_rep_45 (.A(n7222), .B(n2523), .Z(n7703)) /* synthesis lut_function=(A+(B)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(275[5] 292[12])
    defparam i5333_2_lut_rep_45.init = 16'heeee;
    LUT4 i5352_3_lut_else_4_lut (.A(prog[4]), .B(prog[0]), .C(prog[2]), 
         .D(prog[1]), .Z(n7790)) /* synthesis lut_function=(A (C)+!A (B (C)+!B (C (D)))) */ ;
    defparam i5352_3_lut_else_4_lut.init = 16'hf0e0;
    LUT4 i3351_2_lut (.A(ram_out[5]), .B(n1239), .Z(n1604)) /* synthesis lut_function=(A (B)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i3351_2_lut.init = 16'h8888;
    LUT4 mux_29_Mux_0_i31_3_lut_4_lut_then_4_lut (.A(prog[3]), .B(prog[1]), 
         .C(prog[4]), .D(prog[2]), .Z(n7794)) /* synthesis lut_function=(!(A+(B (C+!(D))+!B (C)))) */ ;
    defparam mux_29_Mux_0_i31_3_lut_4_lut_then_4_lut.init = 16'h0501;
    LUT4 i2_3_lut_4_lut (.A(prog[4]), .B(n7986), .C(n4283), .D(n7728), 
         .Z(clk_pll_enable_110)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam i2_3_lut_4_lut.init = 16'h4000;
    LUT4 i3358_4_lut (.A(alu_c[6]), .B(n5236), .C(ram_out[6]), .D(n3170), 
         .Z(n1616)) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i3358_4_lut.init = 16'hc088;
    LUT4 i3352_2_lut (.A(ram_out[6]), .B(n1239), .Z(n1603)) /* synthesis lut_function=(A (B)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i3352_2_lut.init = 16'h8888;
    FD1P3AY led_i0_i3 (.D(A[2]), .SP(clk_pll_enable_33), .CK(clk_pll), 
            .Q(led_c_2));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam led_i0_i3.GSR = "ENABLED";
    FD1P3AY led_i0_i4 (.D(A[3]), .SP(clk_pll_enable_33), .CK(clk_pll), 
            .Q(led_c_3));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam led_i0_i4.GSR = "ENABLED";
    FD1P3AX led_i0_i5 (.D(A[4]), .SP(clk_pll_enable_33), .CK(clk_pll), 
            .Q(led_c_4));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam led_i0_i5.GSR = "ENABLED";
    FD1P3AX led_i0_i6 (.D(A[5]), .SP(clk_pll_enable_33), .CK(clk_pll), 
            .Q(led_c_5));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam led_i0_i6.GSR = "ENABLED";
    FD1P3AX led_i0_i7 (.D(A[6]), .SP(clk_pll_enable_33), .CK(clk_pll), 
            .Q(led_c_6));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam led_i0_i7.GSR = "ENABLED";
    FD1P3AX led_i0_i8 (.D(A[7]), .SP(clk_pll_enable_33), .CK(clk_pll), 
            .Q(led_c_7));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam led_i0_i8.GSR = "ENABLED";
    FD1P3AX A_i0_i1 (.D(A_11__N_225[1]), .SP(clk_pll_enable_44), .CK(clk_pll), 
            .Q(A[1]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam A_i0_i1.GSR = "DISABLED";
    LUT4 mux_29_Mux_0_i31_3_lut_4_lut_else_4_lut (.A(prog[3]), .B(prog[1]), 
         .C(prog[4]), .D(prog[2]), .Z(n7793)) /* synthesis lut_function=(!(A (B)+!A (B (C)+!B (C+!(D))))) */ ;
    defparam mux_29_Mux_0_i31_3_lut_4_lut_else_4_lut.init = 16'h2726;
    FD1P3AX A_i0_i2 (.D(A_11__N_225[2]), .SP(clk_pll_enable_44), .CK(clk_pll), 
            .Q(A[2]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam A_i0_i2.GSR = "DISABLED";
    FD1P3AX A_i0_i3 (.D(A_11__N_225[3]), .SP(clk_pll_enable_44), .CK(clk_pll), 
            .Q(A[3]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam A_i0_i3.GSR = "DISABLED";
    FD1P3AX A_i0_i4 (.D(A_11__N_225[4]), .SP(clk_pll_enable_44), .CK(clk_pll), 
            .Q(A[4]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam A_i0_i4.GSR = "DISABLED";
    FD1P3AX A_i0_i5 (.D(A_11__N_225[5]), .SP(clk_pll_enable_44), .CK(clk_pll), 
            .Q(A[5]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam A_i0_i5.GSR = "DISABLED";
    FD1P3AX A_i0_i6 (.D(A_11__N_225[6]), .SP(clk_pll_enable_44), .CK(clk_pll), 
            .Q(A[6]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam A_i0_i6.GSR = "DISABLED";
    FD1P3AX A_i0_i7 (.D(A_11__N_225[7]), .SP(clk_pll_enable_44), .CK(clk_pll), 
            .Q(A[7]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam A_i0_i7.GSR = "DISABLED";
    FD1P3AX A_i0_i8 (.D(A_11__N_225[8]), .SP(clk_pll_enable_44), .CK(clk_pll), 
            .Q(A[8]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam A_i0_i8.GSR = "DISABLED";
    FD1P3AX A_i0_i9 (.D(A_11__N_225[9]), .SP(clk_pll_enable_44), .CK(clk_pll), 
            .Q(A[9]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam A_i0_i9.GSR = "DISABLED";
    FD1P3AX A_i0_i10 (.D(A_11__N_225[10]), .SP(clk_pll_enable_44), .CK(clk_pll), 
            .Q(A[10]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam A_i0_i10.GSR = "DISABLED";
    FD1P3AX A_i0_i11 (.D(A_11__N_225[11]), .SP(clk_pll_enable_44), .CK(clk_pll), 
            .Q(A[11]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam A_i0_i11.GSR = "DISABLED";
    FD1P3AX B_i0_i1 (.D(alu_c[1]), .SP(clk_pll_enable_55), .CK(clk_pll), 
            .Q(B[1]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam B_i0_i1.GSR = "DISABLED";
    FD1P3AX B_i0_i2 (.D(alu_c[2]), .SP(clk_pll_enable_55), .CK(clk_pll), 
            .Q(B[2]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam B_i0_i2.GSR = "DISABLED";
    FD1P3AX B_i0_i3 (.D(alu_c[3]), .SP(clk_pll_enable_55), .CK(clk_pll), 
            .Q(B[3]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam B_i0_i3.GSR = "DISABLED";
    FD1P3AX B_i0_i4 (.D(alu_c[4]), .SP(clk_pll_enable_55), .CK(clk_pll), 
            .Q(B[4]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam B_i0_i4.GSR = "DISABLED";
    FD1P3AX B_i0_i5 (.D(alu_c[5]), .SP(clk_pll_enable_55), .CK(clk_pll), 
            .Q(B[5]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam B_i0_i5.GSR = "DISABLED";
    FD1P3AX B_i0_i6 (.D(alu_c[6]), .SP(clk_pll_enable_55), .CK(clk_pll), 
            .Q(B[6]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam B_i0_i6.GSR = "DISABLED";
    FD1P3AX B_i0_i7 (.D(alu_c[7]), .SP(clk_pll_enable_55), .CK(clk_pll), 
            .Q(B[7]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam B_i0_i7.GSR = "DISABLED";
    FD1P3AX B_i0_i8 (.D(alu_c[8]), .SP(clk_pll_enable_55), .CK(clk_pll), 
            .Q(B[8]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam B_i0_i8.GSR = "DISABLED";
    FD1P3AX B_i0_i9 (.D(alu_c[9]), .SP(clk_pll_enable_55), .CK(clk_pll), 
            .Q(B[9]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam B_i0_i9.GSR = "DISABLED";
    FD1P3AX B_i0_i10 (.D(alu_c[10]), .SP(clk_pll_enable_55), .CK(clk_pll), 
            .Q(B[10]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam B_i0_i10.GSR = "DISABLED";
    FD1P3AX B_i0_i11 (.D(alu_c[11]), .SP(clk_pll_enable_55), .CK(clk_pll), 
            .Q(B[11]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam B_i0_i11.GSR = "DISABLED";
    FD1P3AX C_i0_i1 (.D(alu_c[1]), .SP(clk_pll_enable_66), .CK(clk_pll), 
            .Q(C[1]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam C_i0_i1.GSR = "DISABLED";
    FD1P3AX C_i0_i2 (.D(alu_c[2]), .SP(clk_pll_enable_66), .CK(clk_pll), 
            .Q(C[2]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam C_i0_i2.GSR = "DISABLED";
    FD1P3AX C_i0_i3 (.D(alu_c[3]), .SP(clk_pll_enable_66), .CK(clk_pll), 
            .Q(C[3]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam C_i0_i3.GSR = "DISABLED";
    FD1P3AX C_i0_i4 (.D(alu_c[4]), .SP(clk_pll_enable_66), .CK(clk_pll), 
            .Q(C[4]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam C_i0_i4.GSR = "DISABLED";
    FD1P3AX C_i0_i5 (.D(alu_c[5]), .SP(clk_pll_enable_66), .CK(clk_pll), 
            .Q(C[5]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam C_i0_i5.GSR = "DISABLED";
    FD1P3AX C_i0_i6 (.D(alu_c[6]), .SP(clk_pll_enable_66), .CK(clk_pll), 
            .Q(C[6]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam C_i0_i6.GSR = "DISABLED";
    FD1P3AX C_i0_i7 (.D(alu_c[7]), .SP(clk_pll_enable_66), .CK(clk_pll), 
            .Q(C[7]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam C_i0_i7.GSR = "DISABLED";
    FD1P3AX C_i0_i8 (.D(alu_c[8]), .SP(clk_pll_enable_66), .CK(clk_pll), 
            .Q(C[8]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam C_i0_i8.GSR = "DISABLED";
    FD1P3AX C_i0_i9 (.D(alu_c[9]), .SP(clk_pll_enable_66), .CK(clk_pll), 
            .Q(C[9]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam C_i0_i9.GSR = "DISABLED";
    FD1P3AX C_i0_i10 (.D(alu_c[10]), .SP(clk_pll_enable_66), .CK(clk_pll), 
            .Q(C[10]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam C_i0_i10.GSR = "DISABLED";
    FD1P3AX C_i0_i11 (.D(alu_c[11]), .SP(clk_pll_enable_66), .CK(clk_pll), 
            .Q(C[11]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam C_i0_i11.GSR = "DISABLED";
    FD1P3AX D_i0_i1 (.D(alu_c[1]), .SP(clk_pll_enable_77), .CK(clk_pll), 
            .Q(D[1]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam D_i0_i1.GSR = "DISABLED";
    FD1P3AX D_i0_i2 (.D(alu_c[2]), .SP(clk_pll_enable_77), .CK(clk_pll), 
            .Q(D[2]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam D_i0_i2.GSR = "DISABLED";
    FD1P3AX D_i0_i3 (.D(alu_c[3]), .SP(clk_pll_enable_77), .CK(clk_pll), 
            .Q(D[3]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam D_i0_i3.GSR = "DISABLED";
    FD1P3AX D_i0_i4 (.D(alu_c[4]), .SP(clk_pll_enable_77), .CK(clk_pll), 
            .Q(D[4]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam D_i0_i4.GSR = "DISABLED";
    FD1P3AX D_i0_i5 (.D(alu_c[5]), .SP(clk_pll_enable_77), .CK(clk_pll), 
            .Q(D[5]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam D_i0_i5.GSR = "DISABLED";
    FD1P3AX D_i0_i6 (.D(alu_c[6]), .SP(clk_pll_enable_77), .CK(clk_pll), 
            .Q(D[6]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam D_i0_i6.GSR = "DISABLED";
    FD1P3AX D_i0_i7 (.D(alu_c[7]), .SP(clk_pll_enable_77), .CK(clk_pll), 
            .Q(D[7]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam D_i0_i7.GSR = "DISABLED";
    FD1P3AX D_i0_i8 (.D(alu_c[8]), .SP(clk_pll_enable_77), .CK(clk_pll), 
            .Q(D[8]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam D_i0_i8.GSR = "DISABLED";
    FD1P3AX D_i0_i9 (.D(alu_c[9]), .SP(clk_pll_enable_77), .CK(clk_pll), 
            .Q(D[9]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam D_i0_i9.GSR = "DISABLED";
    FD1P3AX D_i0_i10 (.D(alu_c[10]), .SP(clk_pll_enable_77), .CK(clk_pll), 
            .Q(D[10]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam D_i0_i10.GSR = "DISABLED";
    FD1P3AX D_i0_i11 (.D(alu_c[11]), .SP(clk_pll_enable_77), .CK(clk_pll), 
            .Q(D[11]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam D_i0_i11.GSR = "DISABLED";
    FD1P3AX alu_b_i0_i1 (.D(n2324), .SP(clk_pll_enable_88), .CK(clk_pll), 
            .Q(alu_b[1]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam alu_b_i0_i1.GSR = "DISABLED";
    LUT4 prog_2__bdd_4_lut_5590 (.A(prog[2]), .B(n5277), .C(n2438), .D(n7727), 
         .Z(n7692)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))+!A (C (D))) */ ;
    defparam prog_2__bdd_4_lut_5590.init = 16'hf088;
    FD1P3AX alu_b_i0_i2 (.D(n2323), .SP(clk_pll_enable_88), .CK(clk_pll), 
            .Q(alu_b[2]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam alu_b_i0_i2.GSR = "DISABLED";
    FD1P3AX alu_b_i0_i3 (.D(n2322), .SP(clk_pll_enable_88), .CK(clk_pll), 
            .Q(alu_b[3]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam alu_b_i0_i3.GSR = "DISABLED";
    FD1P3AX alu_b_i0_i4 (.D(n2321), .SP(clk_pll_enable_88), .CK(clk_pll), 
            .Q(alu_b[4]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam alu_b_i0_i4.GSR = "DISABLED";
    FD1P3AX alu_b_i0_i5 (.D(n2320), .SP(clk_pll_enable_88), .CK(clk_pll), 
            .Q(alu_b[5]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam alu_b_i0_i5.GSR = "DISABLED";
    FD1P3AX alu_b_i0_i6 (.D(n2319), .SP(clk_pll_enable_88), .CK(clk_pll), 
            .Q(alu_b[6]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam alu_b_i0_i6.GSR = "DISABLED";
    FD1P3AX alu_b_i0_i7 (.D(n2318), .SP(clk_pll_enable_88), .CK(clk_pll), 
            .Q(alu_b[7]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam alu_b_i0_i7.GSR = "DISABLED";
    FD1P3AX alu_b_i0_i8 (.D(n2317), .SP(clk_pll_enable_88), .CK(clk_pll), 
            .Q(alu_b[8]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam alu_b_i0_i8.GSR = "DISABLED";
    FD1P3AX alu_b_i0_i9 (.D(n2316), .SP(clk_pll_enable_88), .CK(clk_pll), 
            .Q(alu_b[9]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam alu_b_i0_i9.GSR = "DISABLED";
    FD1P3AX alu_b_i0_i10 (.D(n2315), .SP(clk_pll_enable_88), .CK(clk_pll), 
            .Q(alu_b[10]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam alu_b_i0_i10.GSR = "DISABLED";
    FD1P3AX alu_b_i0_i11 (.D(n2314), .SP(clk_pll_enable_88), .CK(clk_pll), 
            .Q(alu_b[11]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam alu_b_i0_i11.GSR = "DISABLED";
    FD1P3AX ram_in_i0_i1 (.D(A[1]), .SP(clk_pll_enable_99), .CK(clk_pll), 
            .Q(ram_in[1]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam ram_in_i0_i1.GSR = "DISABLED";
    FD1P3AX ram_in_i0_i2 (.D(A[2]), .SP(clk_pll_enable_99), .CK(clk_pll), 
            .Q(ram_in[2]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam ram_in_i0_i2.GSR = "DISABLED";
    FD1P3AX ram_in_i0_i3 (.D(A[3]), .SP(clk_pll_enable_99), .CK(clk_pll), 
            .Q(ram_in[3]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam ram_in_i0_i3.GSR = "DISABLED";
    FD1P3AX ram_in_i0_i4 (.D(A[4]), .SP(clk_pll_enable_99), .CK(clk_pll), 
            .Q(ram_in[4]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam ram_in_i0_i4.GSR = "DISABLED";
    FD1P3AX ram_in_i0_i5 (.D(A[5]), .SP(clk_pll_enable_99), .CK(clk_pll), 
            .Q(ram_in[5]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam ram_in_i0_i5.GSR = "DISABLED";
    FD1P3AX ram_in_i0_i6 (.D(A[6]), .SP(clk_pll_enable_99), .CK(clk_pll), 
            .Q(ram_in[6]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam ram_in_i0_i6.GSR = "DISABLED";
    FD1P3AX ram_in_i0_i7 (.D(A[7]), .SP(clk_pll_enable_99), .CK(clk_pll), 
            .Q(ram_in[7]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam ram_in_i0_i7.GSR = "DISABLED";
    FD1P3AX ram_in_i0_i8 (.D(A[8]), .SP(clk_pll_enable_99), .CK(clk_pll), 
            .Q(ram_in[8]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam ram_in_i0_i8.GSR = "DISABLED";
    FD1P3AX ram_in_i0_i9 (.D(A[9]), .SP(clk_pll_enable_99), .CK(clk_pll), 
            .Q(ram_in[9]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam ram_in_i0_i9.GSR = "DISABLED";
    FD1P3AX ram_in_i0_i10 (.D(A[10]), .SP(clk_pll_enable_99), .CK(clk_pll), 
            .Q(ram_in[10]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam ram_in_i0_i10.GSR = "DISABLED";
    FD1P3AX ram_in_i0_i11 (.D(A[11]), .SP(clk_pll_enable_99), .CK(clk_pll), 
            .Q(ram_in[11]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam ram_in_i0_i11.GSR = "DISABLED";
    FD1P3AX P_i0_i2 (.D(A[1]), .SP(clk_pll_enable_110), .CK(clk_pll), 
            .Q(P_c_1));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam P_i0_i2.GSR = "DISABLED";
    LUT4 i3359_4_lut (.A(alu_c[7]), .B(n5236), .C(ram_out[7]), .D(n3170), 
         .Z(n1615)) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i3359_4_lut.init = 16'hc088;
    PFUMX i1644 (.BLUT(n17_adj_451), .ALUT(PC_9__N_169[1]), .C0(n7264), 
          .Z(n3743));
    FD1P3AX P_i0_i3 (.D(A[2]), .SP(clk_pll_enable_110), .CK(clk_pll), 
            .Q(P_c_2));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam P_i0_i3.GSR = "DISABLED";
    FD1P3AX P_i0_i4 (.D(A[3]), .SP(clk_pll_enable_110), .CK(clk_pll), 
            .Q(P_c_3));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam P_i0_i4.GSR = "DISABLED";
    FD1P3AX P_i0_i5 (.D(A[4]), .SP(clk_pll_enable_110), .CK(clk_pll), 
            .Q(P_c_4));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam P_i0_i5.GSR = "DISABLED";
    FD1P3AX P_i0_i6 (.D(A[5]), .SP(clk_pll_enable_110), .CK(clk_pll), 
            .Q(P_c_5));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam P_i0_i6.GSR = "DISABLED";
    FD1P3AX P_i0_i7 (.D(A[6]), .SP(clk_pll_enable_110), .CK(clk_pll), 
            .Q(P_c_6));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam P_i0_i7.GSR = "DISABLED";
    FD1P3AX P_i0_i8 (.D(A[7]), .SP(clk_pll_enable_110), .CK(clk_pll), 
            .Q(P_c_7));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam P_i0_i8.GSR = "DISABLED";
    FD1P3AX P_i0_i9 (.D(A[8]), .SP(clk_pll_enable_110), .CK(clk_pll), 
            .Q(P_c_8));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam P_i0_i9.GSR = "DISABLED";
    FD1P3AX P_i0_i10 (.D(A[9]), .SP(clk_pll_enable_110), .CK(clk_pll), 
            .Q(P_c_9));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam P_i0_i10.GSR = "DISABLED";
    FD1P3AX P_i0_i11 (.D(A[10]), .SP(clk_pll_enable_110), .CK(clk_pll), 
            .Q(P_c_10));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam P_i0_i11.GSR = "DISABLED";
    FD1P3AX P_i0_i12 (.D(A[11]), .SP(clk_pll_enable_110), .CK(clk_pll), 
            .Q(P_c_11));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam P_i0_i12.GSR = "DISABLED";
    FD1P3AY PC_i0_i1 (.D(n3744), .SP(clk_pll_enable_116), .CK(clk_pll), 
            .Q(PC[1]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam PC_i0_i1.GSR = "ENABLED";
    FD1P3AX PC_i0_i2 (.D(n3746), .SP(clk_pll_enable_116), .CK(clk_pll), 
            .Q(PC[2]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam PC_i0_i2.GSR = "ENABLED";
    FD1P3AX PC_i0_i3 (.D(n3748), .SP(clk_pll_enable_116), .CK(clk_pll), 
            .Q(PC[3]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam PC_i0_i3.GSR = "ENABLED";
    FD1P3AX PC_i0_i4 (.D(n3750), .SP(clk_pll_enable_116), .CK(clk_pll), 
            .Q(PC[4]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam PC_i0_i4.GSR = "ENABLED";
    FD1P3AX PC_i0_i5 (.D(n3752), .SP(clk_pll_enable_116), .CK(clk_pll), 
            .Q(PC[5]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam PC_i0_i5.GSR = "ENABLED";
    FD1P3AX PC_i0_i6 (.D(n3754), .SP(clk_pll_enable_116), .CK(clk_pll), 
            .Q(PC[6]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam PC_i0_i6.GSR = "ENABLED";
    FD1P3AX PC_i0_i7 (.D(n3756), .SP(clk_pll_enable_119), .CK(clk_pll), 
            .Q(PC[7]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam PC_i0_i7.GSR = "ENABLED";
    FD1P3AX PC_i0_i8 (.D(n3758), .SP(clk_pll_enable_119), .CK(clk_pll), 
            .Q(PC[8]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam PC_i0_i8.GSR = "ENABLED";
    FD1P3AX PC_i0_i9 (.D(n3760), .SP(clk_pll_enable_119), .CK(clk_pll), 
            .Q(PC[9]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam PC_i0_i9.GSR = "ENABLED";
    FD1S3AX statu_FSM_i2 (.D(n7712), .CK(clk_pll), .Q(n1241));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam statu_FSM_i2.GSR = "ENABLED";
    PFUMX i1646 (.BLUT(n17_adj_449), .ALUT(PC_9__N_169[2]), .C0(n7264), 
          .Z(n3745));
    LUT4 i5257_3_lut_4_lut_4_lut (.A(n1239), .B(n18_adj_447), .C(n1241), 
         .D(PC_9__N_179[3]), .Z(PC_9__N_169[3])) /* synthesis lut_function=(A (B)+!A (C (D))) */ ;
    defparam i5257_3_lut_4_lut_4_lut.init = 16'hd888;
    LUT4 i3395_2_lut (.A(ram_out[7]), .B(n1239), .Z(n1602)) /* synthesis lut_function=(A (B)) */ ;
    defparam i3395_2_lut.init = 16'h8888;
    FD1S3AX statu_FSM_i4 (.D(n1251), .CK(clk_pll), .Q(n1239));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam statu_FSM_i4.GSR = "ENABLED";
    FD1S3AX statu_FSM_i5 (.D(n1239), .CK(clk_pll), .Q(n1238));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam statu_FSM_i5.GSR = "ENABLED";
    FD1S3AX statu_FSM_i6 (.D(n1238), .CK(clk_pll), .Q(n1237));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam statu_FSM_i6.GSR = "ENABLED";
    FD1P3AX alu_a_i0_i1 (.D(n2296), .SP(clk_pll_enable_130), .CK(clk_pll), 
            .Q(alu_a[1]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam alu_a_i0_i1.GSR = "DISABLED";
    LUT4 i5265_3_lut_4_lut_4_lut (.A(n1239), .B(n18), .C(n1241), .D(PC_9__N_179[6]), 
         .Z(PC_9__N_169[6])) /* synthesis lut_function=(A (B)+!A (C (D))) */ ;
    defparam i5265_3_lut_4_lut_4_lut.init = 16'hd888;
    LUT4 i2406_2_lut_rep_58 (.A(prog[0]), .B(prog[1]), .Z(n7716)) /* synthesis lut_function=(A (B)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam i2406_2_lut_rep_58.init = 16'h8888;
    LUT4 i5222_3_lut_4_lut_4_lut (.A(n1239), .B(n2), .C(n1241), .D(PC_9__N_179[0]), 
         .Z(PC_9__N_169[0])) /* synthesis lut_function=(A (B)+!A (C (D))) */ ;
    defparam i5222_3_lut_4_lut_4_lut.init = 16'hd888;
    LUT4 i3360_4_lut (.A(alu_c[8]), .B(n5236), .C(ram_out[8]), .D(n3170), 
         .Z(n1614)) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i3360_4_lut.init = 16'hc088;
    PFUMX i5526 (.BLUT(n7674), .ALUT(n4273), .C0(prog[4]), .Z(n7675));
    LUT4 mux_722_i5_3_lut (.A(n7705), .B(PC_temp[4]), .C(prog[2]), .Z(n2518)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(275[5] 292[12])
    defparam mux_722_i5_3_lut.init = 16'hcaca;
    LUT4 i3196_3_lut_rep_44 (.A(PC_9__N_179[5]), .B(ram_out[5]), .C(alu_co), 
         .Z(n7702)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(39[6:12])
    defparam i3196_3_lut_rep_44.init = 16'hcaca;
    LUT4 mux_32_Mux_3_i18_3_lut_3_lut (.A(prog[4]), .B(ram_out[3]), .C(D[3]), 
         .Z(n18_adj_447)) /* synthesis lut_function=(A (C)+!A (B)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam mux_32_Mux_3_i18_3_lut_3_lut.init = 16'he4e4;
    LUT4 mux_32_Mux_5_i18_3_lut_3_lut (.A(prog[4]), .B(ram_out[5]), .C(D[5]), 
         .Z(n18_adj_438)) /* synthesis lut_function=(A (C)+!A (B)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam mux_32_Mux_5_i18_3_lut_3_lut.init = 16'he4e4;
    LUT4 mux_32_Mux_2_i18_3_lut_3_lut (.A(prog[4]), .B(ram_out[2]), .C(D[2]), 
         .Z(n18_adj_450)) /* synthesis lut_function=(A (C)+!A (B)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam mux_32_Mux_2_i18_3_lut_3_lut.init = 16'he4e4;
    LUT4 i3125_3_lut (.A(n5227), .B(n235), .C(prog[0]), .Z(n3420)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(29[12:16])
    defparam i3125_3_lut.init = 16'hcaca;
    LUT4 n24_bdd_4_lut_then_2_lut (.A(prog[3]), .B(prog[2]), .Z(n7797)) /* synthesis lut_function=(A+(B)) */ ;
    defparam n24_bdd_4_lut_then_2_lut.init = 16'heeee;
    LUT4 i3394_2_lut (.A(ram_out[8]), .B(n1239), .Z(n1601)) /* synthesis lut_function=(A (B)) */ ;
    defparam i3394_2_lut.init = 16'h8888;
    LUT4 n24_bdd_4_lut_else_2_lut (.A(prog[3]), .B(prog[2]), .C(prog[0]), 
         .D(prog[1]), .Z(n7796)) /* synthesis lut_function=(!(A (B (D))+!A !(B+(C+(D))))) */ ;
    defparam n24_bdd_4_lut_else_2_lut.init = 16'h77fe;
    LUT4 mux_32_Mux_1_i18_3_lut_3_lut (.A(prog[4]), .B(ram_out[1]), .C(D[1]), 
         .Z(n18_adj_452)) /* synthesis lut_function=(A (C)+!A (B)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam mux_32_Mux_1_i18_3_lut_3_lut.init = 16'he4e4;
    LUT4 i1_4_lut (.A(rst_c), .B(n1239), .C(n4557), .D(n4), .Z(clk_pll_enable_44)) /* synthesis lut_function=(!((B (C+!(D))+!B (C))+!A)) */ ;
    defparam i1_4_lut.init = 16'h0a02;
    LUT4 mux_722_i4_3_lut (.A(n7704), .B(PC_temp[3]), .C(prog[2]), .Z(n2519)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(275[5] 292[12])
    defparam mux_722_i4_3_lut.init = 16'hcaca;
    LUT4 i3361_4_lut (.A(alu_c[9]), .B(n5236), .C(ram_out[9]), .D(n3170), 
         .Z(n1613)) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i3361_4_lut.init = 16'hc088;
    LUT4 i1_2_lut_3_lut_4_lut_4_lut (.A(prog[4]), .B(prog[3]), .C(prog[0]), 
         .D(prog[1]), .Z(n7148)) /* synthesis lut_function=(!(A+!(B (C+(D))))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i1_2_lut_3_lut_4_lut_4_lut.init = 16'h4440;
    CCU2D add_178_3 (.A0(SP[1]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(SP[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n6637), 
          .COUT(n6638), .S0(n1186), .S1(n1185));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(181[13:19])
    defparam add_178_3.INIT0 = 16'h5aaa;
    defparam add_178_3.INIT1 = 16'h5aaa;
    defparam add_178_3.INJECT1_0 = "NO";
    defparam add_178_3.INJECT1_1 = "NO";
    LUT4 i3393_2_lut (.A(ram_out[9]), .B(n1239), .Z(n1600)) /* synthesis lut_function=(A (B)) */ ;
    defparam i3393_2_lut.init = 16'h8888;
    LUT4 i656_2_lut_rep_72 (.A(n1239), .B(rst_c), .Z(n7986)) /* synthesis lut_function=(A (B)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i656_2_lut_rep_72.init = 16'h8888;
    LUT4 i3362_4_lut (.A(alu_c[10]), .B(n5236), .C(ram_out[10]), .D(n3170), 
         .Z(n1612)) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i3362_4_lut.init = 16'hc088;
    LUT4 i1_2_lut_4_lut (.A(PC_9__N_179[5]), .B(ram_out[5]), .C(alu_co), 
         .D(prog[2]), .Z(n2491)) /* synthesis lut_function=(A (B (D)+!B !(C+!(D)))+!A (B (C (D)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(39[6:12])
    defparam i1_2_lut_4_lut.init = 16'hca00;
    LUT4 n3203_bdd_3_lut_5367_4_lut_4_lut (.A(prog[4]), .B(prog[3]), .C(prog[1]), 
         .D(prog[0]), .Z(n7425)) /* synthesis lut_function=(!(A ((C (D))+!B))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam n3203_bdd_3_lut_5367_4_lut_4_lut.init = 16'h5ddd;
    LUT4 i3389_2_lut (.A(ram_out[10]), .B(n1239), .Z(n1599)) /* synthesis lut_function=(A (B)) */ ;
    defparam i3389_2_lut.init = 16'h8888;
    LUT4 i2452_3_lut (.A(n4556), .B(n1854), .C(n1237), .Z(n4557)) /* synthesis lut_function=(!(A (B (C))+!A (B+!(C)))) */ ;
    defparam i2452_3_lut.init = 16'h3a3a;
    LUT4 i3363_4_lut (.A(alu_c[11]), .B(n5236), .C(ram_out[11]), .D(n3170), 
         .Z(n1611)) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i3363_4_lut.init = 16'hc088;
    LUT4 i3386_2_lut (.A(ram_out[11]), .B(n1239), .Z(n1598)) /* synthesis lut_function=(A (B)) */ ;
    defparam i3386_2_lut.init = 16'h8888;
    FD1P3AX alu_a_i0_i2 (.D(n2295), .SP(clk_pll_enable_130), .CK(clk_pll), 
            .Q(alu_a[2]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam alu_a_i0_i2.GSR = "DISABLED";
    FD1P3AX alu_a_i0_i3 (.D(n2294), .SP(clk_pll_enable_130), .CK(clk_pll), 
            .Q(alu_a[3]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam alu_a_i0_i3.GSR = "DISABLED";
    FD1P3AX alu_a_i0_i4 (.D(n2293), .SP(clk_pll_enable_130), .CK(clk_pll), 
            .Q(alu_a[4]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam alu_a_i0_i4.GSR = "DISABLED";
    FD1P3AX alu_a_i0_i5 (.D(n2292), .SP(clk_pll_enable_130), .CK(clk_pll), 
            .Q(alu_a[5]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam alu_a_i0_i5.GSR = "DISABLED";
    FD1P3AX alu_a_i0_i6 (.D(n2291), .SP(clk_pll_enable_130), .CK(clk_pll), 
            .Q(alu_a[6]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam alu_a_i0_i6.GSR = "DISABLED";
    FD1P3AX alu_a_i0_i7 (.D(n2290), .SP(clk_pll_enable_130), .CK(clk_pll), 
            .Q(alu_a[7]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam alu_a_i0_i7.GSR = "DISABLED";
    FD1P3AX alu_a_i0_i8 (.D(n2289), .SP(clk_pll_enable_130), .CK(clk_pll), 
            .Q(alu_a[8]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam alu_a_i0_i8.GSR = "DISABLED";
    FD1P3AX alu_a_i0_i9 (.D(n2288), .SP(clk_pll_enable_130), .CK(clk_pll), 
            .Q(alu_a[9]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam alu_a_i0_i9.GSR = "DISABLED";
    FD1P3AX alu_a_i0_i10 (.D(n2287), .SP(clk_pll_enable_130), .CK(clk_pll), 
            .Q(alu_a[10]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam alu_a_i0_i10.GSR = "DISABLED";
    FD1P3AX alu_a_i0_i11 (.D(n2286), .SP(clk_pll_enable_130), .CK(clk_pll), 
            .Q(alu_a[11]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam alu_a_i0_i11.GSR = "DISABLED";
    FD1P3AX PC_temp__0__i2 (.D(n3078), .SP(clk_pll_enable_139), .CK(clk_pll), 
            .Q(PC_temp[1]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam PC_temp__0__i2.GSR = "DISABLED";
    LUT4 mux_647_i1_3_lut (.A(D[0]), .B(A[0]), .C(n11), .Z(n2297)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam mux_647_i1_3_lut.init = 16'hcaca;
    LUT4 i8_3_lut_4_lut (.A(n7713), .B(n7706), .C(D[0]), .D(n3_adj_454), 
         .Z(n2325)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;
    defparam i8_3_lut_4_lut.init = 16'hf780;
    LUT4 mux_651_i2_3_lut_4_lut (.A(n7713), .B(n7706), .C(D[1]), .D(n2310), 
         .Z(n2324)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;
    defparam mux_651_i2_3_lut_4_lut.init = 16'hf780;
    PFUMX i5519 (.BLUT(n7664), .ALUT(n7663), .C0(prog[4]), .Z(n7665));
    LUT4 n3203_bdd_3_lut_5374_4_lut (.A(prog[0]), .B(prog[1]), .C(prog[2]), 
         .D(prog[4]), .Z(n7433)) /* synthesis lut_function=(!(A (B (C+(D))+!B (C))+!A (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam n3203_bdd_3_lut_5374_4_lut.init = 16'h070f;
    LUT4 i2_2_lut_rep_53_3_lut (.A(prog[0]), .B(prog[1]), .C(prog[4]), 
         .Z(n7711)) /* synthesis lut_function=(A (B+(C))+!A (C)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam i2_2_lut_rep_53_3_lut.init = 16'hf8f8;
    LUT4 mux_651_i3_3_lut_4_lut (.A(n7713), .B(n7706), .C(D[2]), .D(n2309), 
         .Z(n2323)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;
    defparam mux_651_i3_3_lut_4_lut.init = 16'hf780;
    LUT4 mux_728_i7_3_lut (.A(n2516), .B(PC_9__N_179[6]), .C(n7222), .Z(n2552)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(275[5] 292[12])
    defparam mux_728_i7_3_lut.init = 16'hcaca;
    LUT4 i3_4_lut (.A(n7721), .B(n7986), .C(prog[2]), .D(n7720), .Z(n11)) /* synthesis lut_function=(A+(((D)+!C)+!B)) */ ;
    defparam i3_4_lut.init = 16'hffbf;
    LUT4 i5339_4_lut (.A(n7710), .B(n1239), .C(prog[2]), .D(prog[4]), 
         .Z(clk_pll_enable_14)) /* synthesis lut_function=(!(A (B)+!A !((C (D))+!B))) */ ;
    defparam i5339_4_lut.init = 16'h7333;
    LUT4 i3340_4_lut (.A(n1242), .B(n1239), .C(IRQ_EN), .D(key_c), .Z(n3351)) /* synthesis lut_function=(A (B+(C (D)))+!A (B+(C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam i3340_4_lut.init = 16'hfcdc;
    LUT4 i1_2_lut_rep_55_3_lut (.A(prog[0]), .B(prog[1]), .C(prog[3]), 
         .Z(n7713)) /* synthesis lut_function=(A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam i1_2_lut_rep_55_3_lut.init = 16'h8080;
    LUT4 mux_651_i5_3_lut_4_lut (.A(n7713), .B(n7706), .C(D[4]), .D(n2307), 
         .Z(n2321)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;
    defparam mux_651_i5_3_lut_4_lut.init = 16'hf780;
    LUT4 i5341_4_lut (.A(rst_c), .B(n1244), .C(n12), .D(n1239), .Z(clk_pll_enable_139)) /* synthesis lut_function=(!((B (C (D))+!B (C+!(D)))+!A)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam i5341_4_lut.init = 16'h0a88;
    LUT4 mux_1194_i1_4_lut (.A(PC[0]), .B(PC_9__N_179[0]), .C(n2361), 
         .D(n1244), .Z(n3079)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam mux_1194_i1_4_lut.init = 16'hcac0;
    LUT4 i277_2_lut (.A(n1241), .B(rst_c), .Z(clk_pll_enable_143)) /* synthesis lut_function=(A (B)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam i277_2_lut.init = 16'h8888;
    PFUMX i1661 (.BLUT(n3759), .ALUT(PC_9__N_159[9]), .C0(n1237), .Z(n3760));
    LUT4 i21_3_lut (.A(prog[2]), .B(prog[1]), .C(prog[0]), .Z(n14_adj_436)) /* synthesis lut_function=(A (B+(C))+!A !(B)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i21_3_lut.init = 16'hb9b9;
    LUT4 i1701_3_lut (.A(n3799), .B(n234), .C(prog[0]), .Z(n3800)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i1701_3_lut.init = 16'hcaca;
    PFUMX i1657 (.BLUT(n3755), .ALUT(PC_9__N_159[7]), .C0(n1237), .Z(n3756));
    LUT4 i3129_4_lut (.A(n469), .B(alu_c[0]), .C(n7727), .D(prog[2]), 
         .Z(n5232)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;
    defparam i3129_4_lut.init = 16'hcac0;
    LUT4 mux_71_i1_3_lut (.A(PC_9__N_179[0]), .B(ram_out[0]), .C(alu_co), 
         .Z(n469)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(284[7:23])
    defparam mux_71_i1_3_lut.init = 16'hcaca;
    PFUMX i1659 (.BLUT(n3757), .ALUT(PC_9__N_159[8]), .C0(n1237), .Z(n3758));
    LUT4 mux_722_i1_3_lut (.A(n469), .B(PC_temp[0]), .C(prog[2]), .Z(n2522)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(275[5] 292[12])
    defparam mux_722_i1_3_lut.init = 16'hcaca;
    LUT4 i1703_3_lut (.A(n3801), .B(n233), .C(prog[0]), .Z(n3802)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i1703_3_lut.init = 16'hcaca;
    LUT4 i1705_3_lut (.A(n3803), .B(n232), .C(prog[0]), .Z(n3804)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i1705_3_lut.init = 16'hcaca;
    LUT4 i1_2_lut_rep_59 (.A(prog[1]), .B(prog[0]), .Z(n7717)) /* synthesis lut_function=(A+(B)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i1_2_lut_rep_59.init = 16'heeee;
    LUT4 i1_3_lut (.A(n1238), .B(n6751), .C(n1237), .Z(n4)) /* synthesis lut_function=(A+(B+(C))) */ ;
    defparam i1_3_lut.init = 16'hfefe;
    LUT4 i11_4_lut (.A(n1244), .B(PC_9__N_179[2]), .C(n2361), .D(PC[2]), 
         .Z(n7013)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i11_4_lut.init = 16'hcac0;
    LUT4 i1_4_lut_else_4_lut_4_lut (.A(n1239), .B(rst_c), .C(prog[2]), 
         .D(prog[4]), .Z(n7748)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i1_4_lut_else_4_lut_4_lut.init = 16'h0800;
    LUT4 i1_2_lut_4_lut_adj_4 (.A(n7708), .B(prog[3]), .C(prog[2]), .D(n7719), 
         .Z(clk_pll_enable_55)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ;
    defparam i1_2_lut_4_lut_adj_4.init = 16'h2000;
    FD1P3AX PC_temp__0__i3 (.D(n7013), .SP(clk_pll_enable_139), .CK(clk_pll), 
            .Q(PC_temp[2]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam PC_temp__0__i3.GSR = "DISABLED";
    FD1P3AX PC_temp__0__i4 (.D(n3076), .SP(clk_pll_enable_139), .CK(clk_pll), 
            .Q(PC_temp[3]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam PC_temp__0__i4.GSR = "DISABLED";
    FD1P3AX PC_temp__0__i5 (.D(n3075), .SP(clk_pll_enable_139), .CK(clk_pll), 
            .Q(PC_temp[4]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam PC_temp__0__i5.GSR = "DISABLED";
    FD1P3AX PC_temp__0__i6 (.D(n3074), .SP(clk_pll_enable_139), .CK(clk_pll), 
            .Q(PC_temp[5]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam PC_temp__0__i6.GSR = "DISABLED";
    FD1P3AX PC_temp__0__i7 (.D(n3073), .SP(clk_pll_enable_139), .CK(clk_pll), 
            .Q(PC_temp[6]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam PC_temp__0__i7.GSR = "DISABLED";
    FD1P3AX PC_temp__0__i8 (.D(n3072), .SP(clk_pll_enable_139), .CK(clk_pll), 
            .Q(PC_temp[7]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam PC_temp__0__i8.GSR = "DISABLED";
    FD1P3AX PC_temp__0__i9 (.D(n3071), .SP(clk_pll_enable_139), .CK(clk_pll), 
            .Q(PC_temp[8]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam PC_temp__0__i9.GSR = "DISABLED";
    FD1P3AX PC_temp__0__i10 (.D(n3070), .SP(clk_pll_enable_139), .CK(clk_pll), 
            .Q(PC_temp[9]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam PC_temp__0__i10.GSR = "DISABLED";
    FD1P3AX prog__1__i2 (.D(ram_out[1]), .SP(clk_pll_enable_143), .CK(clk_pll), 
            .Q(prog[1]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam prog__1__i2.GSR = "DISABLED";
    LUT4 mux_726_i1_4_lut_4_lut_4_lut (.A(prog[4]), .B(n5232), .C(PC_temp[0]), 
         .D(n7711), .Z(n2546)) /* synthesis lut_function=(A (C)+!A (B (C+!(D))+!B (C (D)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam mux_726_i1_4_lut_4_lut_4_lut.init = 16'hf0e4;
    LUT4 seg_dig_0_bdd_2_lut_5524_3_lut_4_lut (.A(n1239), .B(rst_c), .C(prog[4]), 
         .D(n7649), .Z(clk_pll_enable_11)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam seg_dig_0_bdd_2_lut_5524_3_lut_4_lut.init = 16'h8000;
    LUT4 i1707_3_lut (.A(n3805), .B(n231), .C(prog[0]), .Z(n3806)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i1707_3_lut.init = 16'hcaca;
    LUT4 i1709_3_lut (.A(n3807), .B(n230), .C(prog[0]), .Z(n3808)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i1709_3_lut.init = 16'hcaca;
    LUT4 i1_2_lut_4_lut_adj_5 (.A(n7708), .B(prog[3]), .C(prog[2]), .D(n7716), 
         .Z(clk_pll_enable_66)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ;
    defparam i1_2_lut_4_lut_adj_5.init = 16'h2000;
    LUT4 i1_4_lut_4_lut_4_lut_4_lut (.A(prog[3]), .B(prog[1]), .C(prog[0]), 
         .D(prog[4]), .Z(n29)) /* synthesis lut_function=(!(A+!(B+(C (D)+!C !(D))))) */ ;
    defparam i1_4_lut_4_lut_4_lut_4_lut.init = 16'h5445;
    LUT4 i33_2_lut_3_lut (.A(prog[1]), .B(prog[0]), .C(prog[2]), .Z(n12_adj_439)) /* synthesis lut_function=(A (C)+!A (B (C)+!B !(C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i33_2_lut_3_lut.init = 16'he1e1;
    LUT4 i2451_3_lut (.A(n1239), .B(n3246), .C(n1238), .Z(n4556)) /* synthesis lut_function=(A (B (C))+!A (B+!(C))) */ ;
    defparam i2451_3_lut.init = 16'hc5c5;
    LUT4 mux_651_i6_3_lut_4_lut (.A(n7713), .B(n7706), .C(D[5]), .D(n2306), 
         .Z(n2320)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;
    defparam mux_651_i6_3_lut_4_lut.init = 16'hf780;
    LUT4 n7676_bdd_3_lut_4_lut (.A(n3832), .B(n1239), .C(n7675), .D(n1237), 
         .Z(clk_pll_enable_2)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))+!A (C (D))) */ ;
    defparam n7676_bdd_3_lut_4_lut.init = 16'hf088;
    L6MUX21 i1655 (.D0(n3753), .D1(PC_9__N_159[6]), .SD(n1237), .Z(n3754));
    LUT4 mux_651_i7_3_lut_4_lut (.A(n7713), .B(n7706), .C(D[6]), .D(n2305), 
         .Z(n2319)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;
    defparam mux_651_i7_3_lut_4_lut.init = 16'hf780;
    LUT4 i1711_3_lut (.A(n3809), .B(n229), .C(prog[0]), .Z(n3810)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i1711_3_lut.init = 16'hcaca;
    LUT4 i1713_3_lut (.A(n3811), .B(n228), .C(prog[0]), .Z(n3812)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i1713_3_lut.init = 16'hcaca;
    LUT4 mux_1194_i4_4_lut (.A(PC[3]), .B(PC_9__N_179[3]), .C(n2361), 
         .D(n1244), .Z(n3076)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam mux_1194_i4_4_lut.init = 16'hcac0;
    LUT4 i26_3_lut (.A(n7), .B(PC_9__N_179[5]), .C(n7222), .Z(n8)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(29[12:16])
    defparam i26_3_lut.init = 16'hcaca;
    LUT4 i1_4_lut_4_lut_4_lut_then_4_lut (.A(prog[3]), .B(prog[1]), .C(prog[4]), 
         .D(prog[2]), .Z(n7737)) /* synthesis lut_function=(!(A+!(B ((D)+!C)+!B (C (D))))) */ ;
    defparam i1_4_lut_4_lut_4_lut_then_4_lut.init = 16'h5404;
    LUT4 mux_1194_i5_4_lut (.A(PC[4]), .B(PC_9__N_179[4]), .C(n2361), 
         .D(n1244), .Z(n3075)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam mux_1194_i5_4_lut.init = 16'hcac0;
    LUT4 i3165_3_lut (.A(n5266), .B(n227), .C(prog[0]), .Z(n3814)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(29[12:16])
    defparam i3165_3_lut.init = 16'hcaca;
    PFUMX mux_32_Mux_9_i31 (.BLUT(n15_adj_441), .ALUT(n30_adj_443), .C0(prog[4]), 
          .Z(PC_9__N_169[9]));
    LUT4 i52_4_lut (.A(prog[3]), .B(prog[0]), .C(prog[2]), .D(prog[4]), 
         .Z(n31)) /* synthesis lut_function=(!(A (B+!(C (D)))+!A (B (C)+!B !((D)+!C)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i52_4_lut.init = 16'h3505;
    LUT4 i1717_3_lut (.A(n3815), .B(n226), .C(prog[0]), .Z(n3816)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i1717_3_lut.init = 16'hcaca;
    LUT4 n3_bdd_3_lut_4_lut_4_lut (.A(prog[1]), .B(prog[0]), .C(prog[3]), 
         .D(alu_type[1]), .Z(n7456)) /* synthesis lut_function=(!(A ((C)+!B)+!A (B+!(C+(D))))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam n3_bdd_3_lut_4_lut_4_lut.init = 16'h1918;
    LUT4 i1719_3_lut (.A(n3817), .B(n1203), .C(prog[0]), .Z(n3818)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i1719_3_lut.init = 16'hcaca;
    LUT4 i29_4_lut_4_lut (.A(prog[3]), .B(prog[4]), .C(prog[1]), .D(prog[2]), 
         .Z(n12)) /* synthesis lut_function=(A (B+!(C (D)))+!A ((D)+!B)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam i29_4_lut_4_lut.init = 16'hdfbb;
    LUT4 i27_4_lut_4_lut_4_lut (.A(prog[3]), .B(prog[1]), .C(prog[0]), 
         .D(prog[2]), .Z(n14)) /* synthesis lut_function=(!(A ((C+(D))+!B)+!A (B (C+!(D))+!B !(C (D))))) */ ;
    defparam i27_4_lut_4_lut_4_lut.init = 16'h1408;
    PFUMX mux_32_Mux_8_i31 (.BLUT(n15_adj_456), .ALUT(n30_adj_457), .C0(prog[4]), 
          .Z(PC_9__N_169[8]));
    LUT4 i1_4_lut_adj_6 (.A(n7725), .B(D[8]), .C(n7_adj_453), .D(prog[1]), 
         .Z(n30_adj_457)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(29[12:16])
    defparam i1_4_lut_adj_6.init = 16'ha088;
    LUT4 i3419_2_lut (.A(ram_out[8]), .B(n5439), .Z(n15_adj_456)) /* synthesis lut_function=(A (B)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(100[5] 230[13])
    defparam i3419_2_lut.init = 16'h8888;
    LUT4 mux_29_Mux_1_i3_3_lut (.A(alu_type[1]), .B(prog[0]), .C(prog[1]), 
         .Z(n3)) /* synthesis lut_function=(A (B (C)+!B !(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(100[5] 230[13])
    defparam mux_29_Mux_1_i3_3_lut.init = 16'hc2c2;
    LUT4 i3397_4_lut (.A(D[9]), .B(n7725), .C(n17_adj_442), .D(prog[1]), 
         .Z(n30_adj_443)) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(100[5] 230[13])
    defparam i3397_4_lut.init = 16'hc088;
    LUT4 i3364_2_lut (.A(ram_out[9]), .B(n5439), .Z(n15_adj_441)) /* synthesis lut_function=(A (B)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(100[5] 230[13])
    defparam i3364_2_lut.init = 16'h8888;
    LUT4 i3378_2_lut_4_lut (.A(PC_9__N_179[4]), .B(ram_out[4]), .C(alu_co), 
         .D(prog[2]), .Z(n2492)) /* synthesis lut_function=(A (B (D)+!B !(C+!(D)))+!A (B (C (D)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(284[7:23])
    defparam i3378_2_lut_4_lut.init = 16'hca00;
    PFUMX i8 (.BLUT(n5295), .ALUT(n8), .C0(n7703), .Z(n4_adj_444));
    LUT4 i5115_3_lut_4_lut (.A(prog[1]), .B(prog[0]), .C(prog[4]), .D(n7725), 
         .Z(n7210)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i5115_3_lut_4_lut.init = 16'hfeff;
    LUT4 i1658_4_lut (.A(PC_9__N_179[8]), .B(PC_9__N_169[8]), .C(n1239), 
         .D(n1241), .Z(n3757)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i1658_4_lut.init = 16'hcac0;
    LUT4 mux_32_Mux_4_i17_3_lut (.A(SP[4]), .B(n231), .C(prog[0]), .Z(n17_adj_458)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(100[5] 230[13])
    defparam mux_32_Mux_4_i17_3_lut.init = 16'hcaca;
    LUT4 prog_2__bdd_4_lut_5391_4_lut (.A(prog[1]), .B(prog[0]), .C(prog[3]), 
         .D(prog[4]), .Z(n7415)) /* synthesis lut_function=(!(A ((C+!(D))+!B)+!A (B+(C+!(D))))) */ ;
    defparam prog_2__bdd_4_lut_5391_4_lut.init = 16'h0900;
    LUT4 i1656_4_lut (.A(PC_9__N_179[7]), .B(PC_9__N_169[7]), .C(n1239), 
         .D(n1241), .Z(n3755)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i1656_4_lut.init = 16'hcac0;
    LUT4 i1_3_lut_4_lut_4_lut (.A(prog[0]), .B(prog[1]), .C(prog[4]), 
         .D(prog[3]), .Z(n25)) /* synthesis lut_function=(!(A (B (C)+!B !((D)+!C))+!A !(B ((D)+!C)+!B (D)))) */ ;
    defparam i1_3_lut_4_lut_4_lut.init = 16'h7f0e;
    LUT4 i1660_4_lut (.A(PC_9__N_179[9]), .B(PC_9__N_169[9]), .C(n1239), 
         .D(n1241), .Z(n3759)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i1660_4_lut.init = 16'hcac0;
    LUT4 i3_4_lut_adj_7 (.A(prog[0]), .B(n4283), .C(prog[4]), .D(prog[3]), 
         .Z(n6751)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ;
    defparam i3_4_lut_adj_7.init = 16'h0008;
    L6MUX21 i1649 (.D0(n3747), .D1(PC_9__N_159[3]), .SD(n1237), .Z(n3748));
    CCU2D add_178_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(SP[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .COUT(n6637), 
          .S1(n1187));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(181[13:19])
    defparam add_178_1.INIT0 = 16'hF000;
    defparam add_178_1.INIT1 = 16'h5555;
    defparam add_178_1.INJECT1_0 = "NO";
    defparam add_178_1.INJECT1_1 = "NO";
    L6MUX21 i1651 (.D0(n3749), .D1(PC_9__N_159[4]), .SD(n1237), .Z(n3750));
    LUT4 n3203_bdd_4_lut_5469_4_lut (.A(prog[0]), .B(prog[1]), .C(prog[4]), 
         .D(prog[2]), .Z(n7434)) /* synthesis lut_function=(A (B ((D)+!C)+!B (C (D)+!C !(D)))+!A (B ((D)+!C)+!B !(C+!(D)))) */ ;
    defparam n3203_bdd_4_lut_5469_4_lut.init = 16'hed0e;
    LUT4 i1_2_lut_rep_50_3_lut (.A(rst_c), .B(n1238), .C(prog[4]), .Z(n7708)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ;
    defparam i1_2_lut_rep_50_3_lut.init = 16'h0808;
    LUT4 i2_3_lut_4_lut_adj_8 (.A(rst_c), .B(n1238), .C(n14), .D(prog[4]), 
         .Z(clk_pll_enable_12)) /* synthesis lut_function=(A (B (C (D)))) */ ;
    defparam i2_3_lut_4_lut_adj_8.init = 16'h8000;
    LUT4 mux_728_i10_3_lut_else_3_lut (.A(ram_out[9]), .B(PC_9__N_179[9]), 
         .C(n7222), .D(alu_co), .Z(n7739)) /* synthesis lut_function=(A (B+!(C+!(D)))+!A (B (C+!(D)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(275[5] 292[12])
    defparam mux_728_i10_3_lut_else_3_lut.init = 16'hcacc;
    LUT4 mux_649_i2_3_lut_4_lut (.A(n7715), .B(n7706), .C(C[1]), .D(B[1]), 
         .Z(n2310)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam mux_649_i2_3_lut_4_lut.init = 16'hf780;
    LUT4 i1_2_lut_rep_61 (.A(prog[1]), .B(prog[0]), .Z(n7719)) /* synthesis lut_function=(!((B)+!A)) */ ;
    defparam i1_2_lut_rep_61.init = 16'h2222;
    LUT4 prog_4__bdd_4_lut_5583 (.A(prog[1]), .B(prog[3]), .C(prog[2]), 
         .D(prog[0]), .Z(n7649)) /* synthesis lut_function=(!(A (B (C+(D))+!B ((D)+!C))+!A (B+!(C (D))))) */ ;
    defparam prog_4__bdd_4_lut_5583.init = 16'h1028;
    LUT4 i1_2_lut_rep_57_3_lut (.A(prog[1]), .B(prog[0]), .C(prog[3]), 
         .Z(n7715)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ;
    defparam i1_2_lut_rep_57_3_lut.init = 16'h2020;
    LUT4 i5336_3_lut (.A(n1239), .B(prog[4]), .C(prog[1]), .Z(n7264)) /* synthesis lut_function=(!(A (B (C)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i5336_3_lut.init = 16'h7f7f;
    LUT4 equal_59_i7_2_lut_rep_62 (.A(prog[3]), .B(prog[4]), .Z(n7720)) /* synthesis lut_function=(A+!(B)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(266[5:13])
    defparam equal_59_i7_2_lut_rep_62.init = 16'hbbbb;
    LUT4 i6_3_lut (.A(n3751), .B(n4_adj_444), .C(n1237), .Z(n3752)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(29[12:16])
    defparam i6_3_lut.init = 16'hcaca;
    LUT4 i5316_4_lut (.A(n7475), .B(n1240), .C(n4_adj_455), .D(n1238), 
         .Z(clk_pll_enable_119)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ;
    defparam i5316_4_lut.init = 16'h0001;
    LUT4 i5348_3_lut_4_lut (.A(prog[3]), .B(prog[4]), .C(n14_adj_436), 
         .D(n1239), .Z(clk_pll_enable_146)) /* synthesis lut_function=(!(A+((C+!(D))+!B))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(266[5:13])
    defparam i5348_3_lut_4_lut.init = 16'h0400;
    LUT4 i1_2_lut_rep_63 (.A(prog[0]), .B(prog[1]), .Z(n7721)) /* synthesis lut_function=(A+!(B)) */ ;
    defparam i1_2_lut_rep_63.init = 16'hbbbb;
    LUT4 prog_2__bdd_3_lut_5512_4_lut (.A(prog[0]), .B(prog[1]), .C(prog[4]), 
         .D(prog[3]), .Z(n7414)) /* synthesis lut_function=(!(A+((C+!(D))+!B))) */ ;
    defparam prog_2__bdd_3_lut_5512_4_lut.init = 16'h0400;
    PFUMX mux_730_i7 (.BLUT(n2540), .ALUT(n2552), .C0(n7703), .Z(PC_9__N_159[6]));
    LUT4 mux_647_i2_3_lut (.A(D[1]), .B(A[1]), .C(n11), .Z(n2296)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam mux_647_i2_3_lut.init = 16'hcaca;
    LUT4 mux_1194_i6_4_lut (.A(PC[5]), .B(PC_9__N_179[5]), .C(n2361), 
         .D(n1244), .Z(n3074)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam mux_1194_i6_4_lut.init = 16'hcac0;
    PFUMX i5538 (.BLUT(n7733), .ALUT(n7734), .C0(prog[4]), .Z(n3246));
    LUT4 mux_32_Mux_3_i17_3_lut (.A(SP[3]), .B(n232), .C(prog[0]), .Z(n17_adj_446)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(100[5] 230[13])
    defparam mux_32_Mux_3_i17_3_lut.init = 16'hcaca;
    LUT4 mux_728_i9_3_lut_then_3_lut (.A(PC_9__N_179[8]), .B(n7222), .C(PC_temp[8]), 
         .Z(n7743)) /* synthesis lut_function=(A (B+(C))+!A !(B+!(C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(275[5] 292[12])
    defparam mux_728_i9_3_lut_then_3_lut.init = 16'hb8b8;
    LUT4 mux_728_i9_3_lut_else_3_lut (.A(ram_out[8]), .B(PC_9__N_179[8]), 
         .C(n7222), .D(alu_co), .Z(n7742)) /* synthesis lut_function=(A (B+!(C+!(D)))+!A (B (C+!(D)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(275[5] 292[12])
    defparam mux_728_i9_3_lut_else_3_lut.init = 16'hcacc;
    LUT4 mux_728_i8_3_lut_then_3_lut (.A(PC_9__N_179[7]), .B(n7222), .C(PC_temp[7]), 
         .Z(n7746)) /* synthesis lut_function=(A (B+(C))+!A !(B+!(C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(275[5] 292[12])
    defparam mux_728_i8_3_lut_then_3_lut.init = 16'hb8b8;
    LUT4 mux_728_i8_3_lut_else_3_lut (.A(ram_out[7]), .B(PC_9__N_179[7]), 
         .C(n7222), .D(alu_co), .Z(n7745)) /* synthesis lut_function=(A (B+!(C+!(D)))+!A (B (C+!(D)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(275[5] 292[12])
    defparam mux_728_i8_3_lut_else_3_lut.init = 16'hcacc;
    LUT4 i1_4_lut_then_4_lut (.A(prog[3]), .B(prog[2]), .C(prog[0]), .D(prog[1]), 
         .Z(n7734)) /* synthesis lut_function=(A (B+(C (D)))+!A !(B (C+(D)))) */ ;
    defparam i1_4_lut_then_4_lut.init = 16'hb99d;
    LUT4 i1_4_lut_then_4_lut_adj_9 (.A(n7986), .B(prog[4]), .C(prog[2]), 
         .D(prog[1]), .Z(n7749)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i1_4_lut_then_4_lut_adj_9.init = 16'h2000;
    LUT4 i5342_4_lut_then_4_lut (.A(prog[0]), .B(prog[4]), .C(prog[3]), 
         .D(prog[1]), .Z(n7752)) /* synthesis lut_function=(!(A (B (C)+!B (C+!(D)))+!A (B (C+!(D))+!B (C)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i5342_4_lut_then_4_lut.init = 16'h0f09;
    LUT4 i3176_3_lut (.A(PC_9__N_179[2]), .B(ram_out[2]), .C(alu_co), 
         .Z(n5277)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(39[6:12])
    defparam i3176_3_lut.init = 16'hcaca;
    LUT4 i5113_4_lut_4_lut (.A(prog[2]), .B(n7720), .C(n7738), .D(n7986), 
         .Z(n7208)) /* synthesis lut_function=(A (C (D))+!A (B (D)+!B (C (D)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i5113_4_lut_4_lut.init = 16'hf400;
    LUT4 mux_71_i2_3_lut (.A(PC_9__N_179[1]), .B(ram_out[1]), .C(alu_co), 
         .Z(n468)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(284[7:23])
    defparam mux_71_i2_3_lut.init = 16'hcaca;
    LUT4 n25_bdd_4_lut (.A(n25), .B(n29), .C(prog[2]), .D(n7986), .Z(clk_pll_enable_147)) /* synthesis lut_function=(A (B (D)+!B !(C+!(D)))+!A (B (C (D)))) */ ;
    defparam n25_bdd_4_lut.init = 16'hca00;
    LUT4 n7425_bdd_4_lut (.A(n7425), .B(n7424), .C(prog[2]), .D(n7986), 
         .Z(clk_pll_enable_148)) /* synthesis lut_function=(A (B (D)+!B !(C+!(D)))+!A (B (C (D)))) */ ;
    defparam n7425_bdd_4_lut.init = 16'hca00;
    LUT4 i5342_4_lut_else_4_lut (.A(prog[0]), .B(prog[4]), .C(prog[3]), 
         .D(prog[1]), .Z(n7751)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (C))+!A !(B (C)+!B !(C (D)+!C !(D))))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i5342_4_lut_else_4_lut.init = 16'h43d2;
    LUT4 i3177_3_lut (.A(n5277), .B(PC_temp[2]), .C(prog[2]), .Z(n2520)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(29[12:16])
    defparam i3177_3_lut.init = 16'hcaca;
    LUT4 mux_722_i2_3_lut (.A(n468), .B(PC_temp[1]), .C(prog[2]), .Z(n2521)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(275[5] 292[12])
    defparam mux_722_i2_3_lut.init = 16'hcaca;
    LUT4 mux_728_i10_3_lut_then_3_lut (.A(PC_9__N_179[9]), .B(n7222), .C(PC_temp[9]), 
         .Z(n7740)) /* synthesis lut_function=(A (B+(C))+!A !(B+!(C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(275[5] 292[12])
    defparam mux_728_i10_3_lut_then_3_lut.init = 16'hb8b8;
    LUT4 mux_71_i7_3_lut_rep_43 (.A(PC_9__N_179[6]), .B(ram_out[6]), .C(alu_co), 
         .Z(n7701)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(284[7:23])
    defparam mux_71_i7_3_lut_rep_43.init = 16'hcaca;
    LUT4 mux_647_i3_3_lut (.A(D[2]), .B(A[2]), .C(n11), .Z(n2295)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam mux_647_i3_3_lut.init = 16'hcaca;
    PFUMX mux_255_i12 (.BLUT(n1598), .ALUT(n1611), .C0(n1623), .Z(A_11__N_225[11]));
    LUT4 mux_647_i4_3_lut (.A(D[3]), .B(A[3]), .C(n11), .Z(n2294)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam mux_647_i4_3_lut.init = 16'hcaca;
    LUT4 mux_647_i5_3_lut (.A(D[4]), .B(A[4]), .C(n11), .Z(n2293)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam mux_647_i5_3_lut.init = 16'hcaca;
    LUT4 i1_4_lut_else_4_lut (.A(prog[3]), .B(prog[2]), .C(prog[0]), .D(prog[1]), 
         .Z(n7733)) /* synthesis lut_function=((B+!(C+(D)))+!A) */ ;
    defparam i1_4_lut_else_4_lut.init = 16'hdddf;
    LUT4 mux_647_i6_3_lut (.A(D[5]), .B(A[5]), .C(n11), .Z(n2292)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam mux_647_i6_3_lut.init = 16'hcaca;
    FD1P3AX prog__1__i3 (.D(ram_out[2]), .SP(clk_pll_enable_143), .CK(clk_pll), 
            .Q(prog[2]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam prog__1__i3.GSR = "DISABLED";
    FD1P3AX prog__1__i4 (.D(ram_out[3]), .SP(clk_pll_enable_143), .CK(clk_pll), 
            .Q(prog[3]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam prog__1__i4.GSR = "DISABLED";
    FD1P3AX prog__1__i5 (.D(ram_out[4]), .SP(clk_pll_enable_143), .CK(clk_pll), 
            .Q(prog[4]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam prog__1__i5.GSR = "DISABLED";
    LUT4 mux_1194_i7_4_lut (.A(PC[6]), .B(PC_9__N_179[6]), .C(n2361), 
         .D(n1244), .Z(n3073)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam mux_1194_i7_4_lut.init = 16'hcac0;
    PFUMX mux_255_i11 (.BLUT(n1599), .ALUT(n1612), .C0(n1623), .Z(A_11__N_225[10]));
    LUT4 mux_647_i7_3_lut (.A(D[6]), .B(A[6]), .C(n11), .Z(n2291)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam mux_647_i7_3_lut.init = 16'hcaca;
    LUT4 mux_647_i8_3_lut (.A(D[7]), .B(A[7]), .C(n11), .Z(n2290)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam mux_647_i8_3_lut.init = 16'hcaca;
    LUT4 i3166_3_lut (.A(D[8]), .B(A[8]), .C(n11), .Z(n2289)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i3166_3_lut.init = 16'hcaca;
    LUT4 mux_647_i10_3_lut (.A(D[9]), .B(A[9]), .C(n11), .Z(n2288)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam mux_647_i10_3_lut.init = 16'hcaca;
    PFUMX i5400 (.BLUT(n7985), .ALUT(n7145), .C0(n1237), .Z(n7475));
    PFUMX mux_255_i10 (.BLUT(n1600), .ALUT(n1613), .C0(n1623), .Z(A_11__N_225[9]));
    LUT4 i2463_1_lut (.A(n1241), .Z(n4568)) /* synthesis lut_function=(!(A)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i2463_1_lut.init = 16'h5555;
    LUT4 mux_1194_i8_4_lut (.A(PC[7]), .B(PC_9__N_179[7]), .C(n2361), 
         .D(n1244), .Z(n3072)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam mux_1194_i8_4_lut.init = 16'hcac0;
    LUT4 i3370_2_lut_2_lut (.A(prog[4]), .B(alu_c[6]), .Z(n2434)) /* synthesis lut_function=(!(A+!(B))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i3370_2_lut_2_lut.init = 16'h4444;
    LUT4 i3371_2_lut_2_lut (.A(prog[4]), .B(alu_c[7]), .Z(n2433)) /* synthesis lut_function=(!(A+!(B))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i3371_2_lut_2_lut.init = 16'h4444;
    PFUMX mux_255_i9 (.BLUT(n1601), .ALUT(n1614), .C0(n1623), .Z(A_11__N_225[8]));
    LUT4 i3372_2_lut_2_lut (.A(prog[4]), .B(alu_c[8]), .Z(n2432)) /* synthesis lut_function=(!(A+!(B))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i3372_2_lut_2_lut.init = 16'h4444;
    LUT4 mux_728_i2_3_lut (.A(n2521), .B(PC_9__N_179[1]), .C(n7222), .Z(n2557)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(275[5] 292[12])
    defparam mux_728_i2_3_lut.init = 16'hcaca;
    LUT4 mux_1194_i9_4_lut (.A(PC[8]), .B(PC_9__N_179[8]), .C(n2361), 
         .D(n1244), .Z(n3071)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam mux_1194_i9_4_lut.init = 16'hcac0;
    LUT4 i3373_2_lut_2_lut (.A(prog[4]), .B(alu_c[9]), .Z(n2431)) /* synthesis lut_function=(!(A+!(B))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i3373_2_lut_2_lut.init = 16'h4444;
    LUT4 i5346_4_lut (.A(prog[4]), .B(prog[3]), .C(prog[0]), .D(n7123), 
         .Z(clk_pll_enable_33)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam i5346_4_lut.init = 16'h0004;
    PFUMX i5578 (.BLUT(n7793), .ALUT(n7794), .C0(prog[0]), .Z(n7795));
    LUT4 i2007_2_lut_3_lut (.A(n1239), .B(rst_c), .C(n3832), .Z(clk_pll_enable_99)) /* synthesis lut_function=(A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i2007_2_lut_3_lut.init = 16'h8080;
    CCU2D add_179_7 (.A0(PC[5]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(PC[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n6628), 
          .COUT(n6629), .S0(PC_9__N_179[5]), .S1(PC_9__N_179[6]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(184[18:27])
    defparam add_179_7.INIT0 = 16'h5aaa;
    defparam add_179_7.INIT1 = 16'h5aaa;
    defparam add_179_7.INJECT1_0 = "NO";
    defparam add_179_7.INJECT1_1 = "NO";
    LUT4 i1_2_lut_rep_48_3_lut_4_lut (.A(n1239), .B(rst_c), .C(prog[2]), 
         .D(prog[4]), .Z(n7706)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i1_2_lut_rep_48_3_lut_4_lut.init = 16'h0008;
    LUT4 mux_1194_i10_4_lut (.A(PC[9]), .B(PC_9__N_179[9]), .C(n2361), 
         .D(n1244), .Z(n3070)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam mux_1194_i10_4_lut.init = 16'hcac0;
    LUT4 mux_728_i3_3_lut (.A(n2520), .B(PC_9__N_179[2]), .C(n7222), .Z(n2556)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(275[5] 292[12])
    defparam mux_728_i3_3_lut.init = 16'hcaca;
    CCU2D add_179_5 (.A0(PC[3]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(PC[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n6627), 
          .COUT(n6628), .S0(PC_9__N_179[3]), .S1(PC_9__N_179[4]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(184[18:27])
    defparam add_179_5.INIT0 = 16'h5aaa;
    defparam add_179_5.INIT1 = 16'h5aaa;
    defparam add_179_5.INJECT1_0 = "NO";
    defparam add_179_5.INJECT1_1 = "NO";
    LUT4 i1_2_lut (.A(prog[2]), .B(prog[1]), .Z(n4283)) /* synthesis lut_function=(!((B)+!A)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i1_2_lut.init = 16'h2222;
    PFUMX mux_255_i8 (.BLUT(n1602), .ALUT(n1615), .C0(n1623), .Z(A_11__N_225[7]));
    LUT4 i5304_3_lut_4_lut (.A(n7222), .B(n2523), .C(n7744), .D(n2538), 
         .Z(PC_9__N_159[8])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(275[5] 292[12])
    defparam i5304_3_lut_4_lut.init = 16'hf1e0;
    LUT4 i3382_2_lut_4_lut (.A(PC_9__N_179[9]), .B(ram_out[9]), .C(alu_co), 
         .D(prog[2]), .Z(n2487)) /* synthesis lut_function=(A (B (D)+!B !(C+!(D)))+!A (B (C (D)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(284[7:23])
    defparam i3382_2_lut_4_lut.init = 16'hca00;
    CCU2D sub_181_add_2_11 (.A0(SP[9]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(SP[10]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n6635), 
          .S0(n226), .S1(n1203));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(186[13:19])
    defparam sub_181_add_2_11.INIT0 = 16'h5555;
    defparam sub_181_add_2_11.INIT1 = 16'h5555;
    defparam sub_181_add_2_11.INJECT1_0 = "NO";
    defparam sub_181_add_2_11.INJECT1_1 = "NO";
    LUT4 i5308_3_lut_4_lut (.A(n7222), .B(n2523), .C(n7741), .D(n2537), 
         .Z(PC_9__N_159[9])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(275[5] 292[12])
    defparam i5308_3_lut_4_lut.init = 16'hf1e0;
    LUT4 i3366_2_lut_2_lut (.A(prog[4]), .B(alu_c[2]), .Z(n2438)) /* synthesis lut_function=(!(A+!(B))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i3366_2_lut_2_lut.init = 16'h4444;
    LUT4 i7_3_lut_4_lut (.A(n7715), .B(n7706), .C(C[0]), .D(B[0]), .Z(n3_adj_454)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam i7_3_lut_4_lut.init = 16'hf780;
    LUT4 i1702_3_lut_4_lut (.A(n7123), .B(n7720), .C(n1185), .D(A[2]), 
         .Z(n3801)) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;
    defparam i1702_3_lut_4_lut.init = 16'hf1e0;
    LUT4 i1704_3_lut_4_lut (.A(n7123), .B(n7720), .C(n1184), .D(A[3]), 
         .Z(n3803)) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;
    defparam i1704_3_lut_4_lut.init = 16'hf1e0;
    LUT4 i4_4_lut (.A(n7_adj_445), .B(n7726), .C(n1240), .D(n6), .Z(clk_pll_enable_116)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ;
    defparam i4_4_lut.init = 16'h0002;
    LUT4 i2_4_lut_adj_10 (.A(n1237), .B(n7712), .C(n7529), .D(n1239), 
         .Z(n7_adj_445)) /* synthesis lut_function=(!(A (B)+!A (B+!(C+!(D))))) */ ;
    defparam i2_4_lut_adj_10.init = 16'h3233;
    LUT4 i1700_3_lut_4_lut (.A(n7123), .B(n7720), .C(n1186), .D(A[1]), 
         .Z(n3799)) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;
    defparam i1700_3_lut_4_lut.init = 16'hf1e0;
    LUT4 mux_32_Mux_6_i17_3_lut (.A(SP[6]), .B(n229), .C(prog[0]), .Z(n17)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(100[5] 230[13])
    defparam mux_32_Mux_6_i17_3_lut.init = 16'hcaca;
    PFUMX mux_255_i7 (.BLUT(n1603), .ALUT(n1616), .C0(n1623), .Z(A_11__N_225[6]));
    LUT4 i1706_3_lut_4_lut (.A(n7123), .B(n7720), .C(n1183), .D(A[4]), 
         .Z(n3805)) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;
    defparam i1706_3_lut_4_lut.init = 16'hf1e0;
    LUT4 mux_649_i3_3_lut_4_lut (.A(n7715), .B(n7706), .C(C[2]), .D(B[2]), 
         .Z(n2309)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam mux_649_i3_3_lut_4_lut.init = 16'hf780;
    LUT4 i1_3_lut_adj_11 (.A(n1237), .B(n1238), .C(n7145), .Z(n6)) /* synthesis lut_function=(A (B+(C))+!A (B)) */ ;
    defparam i1_3_lut_adj_11.init = 16'hecec;
    LUT4 i1708_3_lut_4_lut (.A(n7123), .B(n7720), .C(n1182), .D(A[5]), 
         .Z(n3807)) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;
    defparam i1708_3_lut_4_lut.init = 16'hf1e0;
    LUT4 mux_32_Mux_5_i17_3_lut (.A(SP[5]), .B(n230), .C(prog[0]), .Z(n17_adj_437)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(100[5] 230[13])
    defparam mux_32_Mux_5_i17_3_lut.init = 16'hcaca;
    LUT4 mux_649_i4_3_lut_4_lut (.A(n7715), .B(n7706), .C(C[3]), .D(B[3]), 
         .Z(n2308)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam mux_649_i4_3_lut_4_lut.init = 16'hf780;
    LUT4 mux_649_i5_3_lut_4_lut (.A(n7715), .B(n7706), .C(C[4]), .D(B[4]), 
         .Z(n2307)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam mux_649_i5_3_lut_4_lut.init = 16'hf780;
    LUT4 i1710_3_lut_4_lut (.A(n7123), .B(n7720), .C(n1181), .D(A[6]), 
         .Z(n3809)) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;
    defparam i1710_3_lut_4_lut.init = 16'hf1e0;
    LUT4 mux_651_i8_3_lut_4_lut (.A(n7713), .B(n7706), .C(D[7]), .D(n2304), 
         .Z(n2318)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;
    defparam mux_651_i8_3_lut_4_lut.init = 16'hf780;
    PFUMX mux_255_i6 (.BLUT(n1604), .ALUT(n1617), .C0(n1623), .Z(A_11__N_225[5]));
    LUT4 i1_2_lut_rep_52_3_lut (.A(prog[1]), .B(prog[3]), .C(prog[0]), 
         .Z(n7710)) /* synthesis lut_function=(A+((C)+!B)) */ ;
    defparam i1_2_lut_rep_52_3_lut.init = 16'hfbfb;
    PFUMX i5576 (.BLUT(n7790), .ALUT(n7791), .C0(prog[3]), .Z(n7222));
    LUT4 i1_3_lut_4_lut_4_lut_4_lut (.A(prog[3]), .B(prog[0]), .C(prog[1]), 
         .D(prog[2]), .Z(n16)) /* synthesis lut_function=(!(A (((D)+!C)+!B)+!A (D))) */ ;
    defparam i1_3_lut_4_lut_4_lut_4_lut.init = 16'h00d5;
    LUT4 i5306_3_lut_4_lut (.A(n7222), .B(n2523), .C(n7747), .D(n2539), 
         .Z(PC_9__N_159[7])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(275[5] 292[12])
    defparam i5306_3_lut_4_lut.init = 16'hf1e0;
    LUT4 n468_bdd_4_lut (.A(n468), .B(prog[2]), .C(n2439), .D(n7727), 
         .Z(n7693)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))+!A (C (D))) */ ;
    defparam n468_bdd_4_lut.init = 16'hf088;
    PFUMX mux_255_i5 (.BLUT(n1605), .ALUT(n1618), .C0(n1623), .Z(A_11__N_225[4]));
    LUT4 mux_32_Mux_9_i17_3_lut (.A(SP[9]), .B(n226), .C(prog[0]), .Z(n17_adj_442)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(100[5] 230[13])
    defparam mux_32_Mux_9_i17_3_lut.init = 16'hcaca;
    LUT4 i8_3_lut (.A(SP[8]), .B(n227), .C(prog[0]), .Z(n7_adj_453)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(29[12:16])
    defparam i8_3_lut.init = 16'hcaca;
    LUT4 i25_3_lut (.A(n7702), .B(PC_temp[5]), .C(prog[2]), .Z(n7)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(29[12:16])
    defparam i25_3_lut.init = 16'hcaca;
    PFUMX i28 (.BLUT(n12_adj_439), .ALUT(n16), .C0(prog[4]), .Z(n7071));
    LUT4 i1712_3_lut_4_lut (.A(n7123), .B(n7720), .C(n1180), .D(A[7]), 
         .Z(n3811)) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;
    defparam i1712_3_lut_4_lut.init = 16'hf1e0;
    LUT4 mux_722_i7_3_lut (.A(n7701), .B(PC_temp[6]), .C(prog[2]), .Z(n2516)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(275[5] 292[12])
    defparam mux_722_i7_3_lut.init = 16'hcaca;
    LUT4 i2_3_lut (.A(n1239), .B(prog[2]), .C(prog[1]), .Z(n7123)) /* synthesis lut_function=(((C)+!B)+!A) */ ;
    defparam i2_3_lut.init = 16'hf7f7;
    LUT4 i3164_3_lut_4_lut (.A(n7123), .B(n7720), .C(n1179), .D(A[8]), 
         .Z(n5266)) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;
    defparam i3164_3_lut_4_lut.init = 16'hf1e0;
    LUT4 i1716_3_lut_4_lut (.A(n7123), .B(n7720), .C(n1178), .D(A[9]), 
         .Z(n3815)) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;
    defparam i1716_3_lut_4_lut.init = 16'hf1e0;
    LUT4 i1718_3_lut_4_lut (.A(n7123), .B(n7720), .C(n1177), .D(A[10]), 
         .Z(n3817)) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;
    defparam i1718_3_lut_4_lut.init = 16'hf1e0;
    LUT4 i1_4_lut_4_lut_4_lut_else_4_lut (.A(prog[3]), .B(prog[1]), .C(prog[4]), 
         .D(prog[2]), .Z(n7736)) /* synthesis lut_function=(!(A+!(B ((D)+!C)+!B !(C)))) */ ;
    defparam i1_4_lut_4_lut_4_lut_else_4_lut.init = 16'h4505;
    PFUMX mux_255_i4 (.BLUT(n1606), .ALUT(n1619), .C0(n1623), .Z(A_11__N_225[3]));
    LUT4 n7434_bdd_4_lut (.A(n7434), .B(n7433), .C(prog[3]), .D(n7986), 
         .Z(clk_pll_enable_145)) /* synthesis lut_function=(A (B (D)+!B !(C+!(D)))+!A (B (C (D)))) */ ;
    defparam n7434_bdd_4_lut.init = 16'hca00;
    PFUMX mux_255_i3 (.BLUT(n1607), .ALUT(n1620), .C0(n1623), .Z(A_11__N_225[2]));
    LUT4 i3124_3_lut_4_lut (.A(n7123), .B(n7720), .C(n1187), .D(A[0]), 
         .Z(n5227)) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;
    defparam i3124_3_lut_4_lut.init = 16'hf1e0;
    PFUMX mux_255_i2 (.BLUT(n1608), .ALUT(n1621), .C0(n1623), .Z(A_11__N_225[1]));
    PFUMX mux_1135_i10 (.BLUT(n2487), .ALUT(n2431), .C0(n7727), .Z(n3213));
    LUT4 i3379_2_lut_4_lut (.A(PC_9__N_179[6]), .B(ram_out[6]), .C(alu_co), 
         .D(prog[2]), .Z(n2490)) /* synthesis lut_function=(A (B (D)+!B !(C+!(D)))+!A (B (C (D)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(284[7:23])
    defparam i3379_2_lut_4_lut.init = 16'hca00;
    LUT4 n7796_bdd_4_lut (.A(n7796), .B(n7797), .C(prog[4]), .D(n1239), 
         .Z(n7985)) /* synthesis lut_function=(A (B (D)+!B !(C+!(D)))+!A (B (C (D)))) */ ;
    defparam n7796_bdd_4_lut.init = 16'hca00;
    PFUMX mux_32_Mux_7_i31 (.BLUT(n15), .ALUT(n30), .C0(prog[4]), .Z(PC_9__N_169[7]));
    LUT4 prog_3__bdd_3_lut_3_lut (.A(prog[4]), .B(prog[1]), .C(prog[2]), 
         .Z(n7527)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam prog_3__bdd_3_lut_3_lut.init = 16'h4040;
    LUT4 mux_728_i4_3_lut (.A(n2519), .B(PC_9__N_179[3]), .C(n7222), .Z(n2555)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(275[5] 292[12])
    defparam mux_728_i4_3_lut.init = 16'hcaca;
    PFUMX mux_255_i1 (.BLUT(n1609), .ALUT(n1622), .C0(n1623), .Z(A_11__N_225[0]));
    PFUMX i1310 (.BLUT(n1), .ALUT(PC_9__N_169[0]), .C0(n7264), .Z(n3409));
    FD1P3AX alu_type_i0_i0 (.D(n7795), .SP(clk_pll_enable_144), .CK(clk_pll), 
            .Q(alu_type[0]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam alu_type_i0_i0.GSR = "DISABLED";
    LUT4 mux_728_i5_3_lut (.A(n2518), .B(PC_9__N_179[4]), .C(n7222), .Z(n2554)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(275[5] 292[12])
    defparam mux_728_i5_3_lut.init = 16'hcaca;
    LUT4 i4_4_lut_adj_12 (.A(n7196), .B(n7711), .C(prog[2]), .D(n7222), 
         .Z(n7145)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ;
    defparam i4_4_lut_adj_12.init = 16'h0001;
    LUT4 mux_726_i2_3_lut_4_lut (.A(n7716), .B(prog[4]), .C(PC_temp[1]), 
         .D(n7693), .Z(n2545)) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;
    defparam mux_726_i2_3_lut_4_lut.init = 16'hf1e0;
    CCU2D sub_181_add_2_9 (.A0(SP[7]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(SP[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n6634), 
          .COUT(n6635), .S0(n228), .S1(n227));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(186[13:19])
    defparam sub_181_add_2_9.INIT0 = 16'h5555;
    defparam sub_181_add_2_9.INIT1 = 16'h5555;
    defparam sub_181_add_2_9.INJECT1_0 = "NO";
    defparam sub_181_add_2_9.INJECT1_1 = "NO";
    L6MUX21 i1645 (.D0(n3743), .D1(PC_9__N_159[1]), .SD(n1237), .Z(n3744));
    FD1P3AX alu_type_i0_i3 (.D(n7148), .SP(clk_pll_enable_145), .CK(clk_pll), 
            .Q(alu_type[3]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam alu_type_i0_i3.GSR = "DISABLED";
    LUT4 i3163_3_lut_4_lut (.A(n7713), .B(n7706), .C(D[8]), .D(n5264), 
         .Z(n2317)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;
    defparam i3163_3_lut_4_lut.init = 16'hf780;
    LUT4 mux_32_Mux_2_i17_3_lut (.A(SP[2]), .B(n233), .C(prog[0]), .Z(n17_adj_449)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(100[5] 230[13])
    defparam mux_32_Mux_2_i17_3_lut.init = 16'hcaca;
    L6MUX21 i1647 (.D0(n3745), .D1(PC_9__N_159[2]), .SD(n1237), .Z(n3746));
    LUT4 prog_0__bdd_3_lut_4_lut (.A(prog[3]), .B(prog[2]), .C(prog[1]), 
         .D(prog[0]), .Z(n7674)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(265[5] 272[12])
    defparam prog_0__bdd_3_lut_4_lut.init = 16'h8000;
    PFUMX mux_730_i5 (.BLUT(n2542), .ALUT(n2554), .C0(n7703), .Z(PC_9__N_159[4]));
    FD1P3AX SP_i0_i0 (.D(n3420), .SP(clk_pll_enable_146), .CK(clk_pll), 
            .Q(SP[0]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam SP_i0_i0.GSR = "ENABLED";
    LUT4 mux_32_Mux_1_i17_3_lut (.A(SP[1]), .B(n234), .C(prog[0]), .Z(n17_adj_451)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(100[5] 230[13])
    defparam mux_32_Mux_1_i17_3_lut.init = 16'hcaca;
    LUT4 mux_651_i12_3_lut_4_lut (.A(n7713), .B(n7706), .C(D[11]), .D(n2300), 
         .Z(n2314)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;
    defparam mux_651_i12_3_lut_4_lut.init = 16'hf780;
    CCU2D sub_181_add_2_7 (.A0(SP[5]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(SP[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n6633), 
          .COUT(n6634), .S0(n230), .S1(n229));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(186[13:19])
    defparam sub_181_add_2_7.INIT0 = 16'h5555;
    defparam sub_181_add_2_7.INIT1 = 16'h5555;
    defparam sub_181_add_2_7.INJECT1_0 = "NO";
    defparam sub_181_add_2_7.INJECT1_1 = "NO";
    PFUMX mux_730_i4 (.BLUT(n2543), .ALUT(n2555), .C0(n7703), .Z(PC_9__N_159[3]));
    LUT4 mux_726_i8_3_lut_4_lut (.A(n7716), .B(prog[4]), .C(PC_temp[7]), 
         .D(n3211), .Z(n2539)) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;
    defparam mux_726_i8_3_lut_4_lut.init = 16'hf1e0;
    LUT4 i5_3_lut (.A(SP[0]), .B(n235), .C(prog[0]), .Z(n1)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(29[12:16])
    defparam i5_3_lut.init = 16'hcaca;
    LUT4 mux_726_i4_3_lut_4_lut (.A(n7716), .B(prog[4]), .C(PC_temp[3]), 
         .D(n3207), .Z(n2543)) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;
    defparam mux_726_i4_3_lut_4_lut.init = 16'hf1e0;
    LUT4 i1_2_lut_rep_66 (.A(alu_type[1]), .B(alu_type[0]), .Z(n7724)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i1_2_lut_rep_66.init = 16'heeee;
    LUT4 mux_649_i6_3_lut_4_lut (.A(n7715), .B(n7706), .C(C[5]), .D(B[5]), 
         .Z(n2306)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam mux_649_i6_3_lut_4_lut.init = 16'hf780;
    PFUMX i1697 (.BLUT(n7674), .ALUT(n4273), .C0(prog[4]), .Z(n3832));
    FD1P3AX alu_type_i0_i2 (.D(n7665), .SP(clk_pll_enable_147), .CK(clk_pll), 
            .Q(alu_type[2]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam alu_type_i0_i2.GSR = "DISABLED";
    LUT4 i2414_1_lut (.A(n1237), .Z(n4518)) /* synthesis lut_function=(!(A)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i2414_1_lut.init = 16'h5555;
    LUT4 i5329_3_lut_4_lut (.A(alu_type[1]), .B(alu_type[0]), .C(alu_type[3]), 
         .D(alu_type[2]), .Z(R_11__N_429)) /* synthesis lut_function=(A (C+!(D))+!A ((C+!(D))+!B)) */ ;
    defparam i5329_3_lut_4_lut.init = 16'hf1ff;
    LUT4 i1_3_lut_4_lut (.A(alu_type[1]), .B(alu_type[0]), .C(alu_type[2]), 
         .D(alu_type[3]), .Z(Co_N_435)) /* synthesis lut_function=(!(A ((D)+!C)+!A (B ((D)+!C)+!B (C+(D))))) */ ;
    defparam i1_3_lut_4_lut.init = 16'h00e1;
    LUT4 i6_3_lut_3_lut (.A(prog[4]), .B(ram_out[0]), .C(D[0]), .Z(n2)) /* synthesis lut_function=(A (C)+!A (B)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i6_3_lut_3_lut.init = 16'he4e4;
    LUT4 i3381_2_lut_4_lut (.A(PC_9__N_179[8]), .B(ram_out[8]), .C(alu_co), 
         .D(prog[2]), .Z(n2488)) /* synthesis lut_function=(A (B (D)+!B !(C+!(D)))+!A (B (C (D)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(284[7:23])
    defparam i3381_2_lut_4_lut.init = 16'hca00;
    CCU2D add_179_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(PC[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .COUT(n6626), 
          .S1(PC_9__N_179[0]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(184[18:27])
    defparam add_179_1.INIT0 = 16'hF000;
    defparam add_179_1.INIT1 = 16'h5555;
    defparam add_179_1.INJECT1_0 = "NO";
    defparam add_179_1.INJECT1_1 = "NO";
    LUT4 mux_649_i7_3_lut_4_lut (.A(n7715), .B(n7706), .C(C[6]), .D(B[6]), 
         .Z(n2305)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam mux_649_i7_3_lut_4_lut.init = 16'hf780;
    LUT4 i5324_2_lut_rep_67 (.A(prog[2]), .B(prog[3]), .Z(n7725)) /* synthesis lut_function=(!(A+(B))) */ ;
    defparam i5324_2_lut_rep_67.init = 16'h1111;
    PFUMX mux_1135_i9 (.BLUT(n2488), .ALUT(n2432), .C0(n7727), .Z(n3212));
    LUT4 i3367_2_lut_2_lut (.A(prog[4]), .B(alu_c[3]), .Z(n2437)) /* synthesis lut_function=(!(A+!(B))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i3367_2_lut_2_lut.init = 16'h4444;
    CCU2D sub_181_add_2_5 (.A0(SP[3]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(SP[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n6632), 
          .COUT(n6633), .S0(n232), .S1(n231));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(186[13:19])
    defparam sub_181_add_2_5.INIT0 = 16'h5555;
    defparam sub_181_add_2_5.INIT1 = 16'h5555;
    defparam sub_181_add_2_5.INJECT1_0 = "NO";
    defparam sub_181_add_2_5.INJECT1_1 = "NO";
    PFUMX i5389 (.BLUT(n7457), .ALUT(n7456), .C0(prog[4]), .Z(n7458));
    LUT4 i1113_2_lut (.A(n1237), .B(n1854), .Z(n3170)) /* synthesis lut_function=(A (B)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i1113_2_lut.init = 16'h8888;
    PFUMX mux_1135_i8 (.BLUT(n2489), .ALUT(n2433), .C0(n7727), .Z(n3211));
    LUT4 mux_71_i5_3_lut_rep_47 (.A(PC_9__N_179[4]), .B(ram_out[4]), .C(alu_co), 
         .Z(n7705)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(284[7:23])
    defparam mux_71_i5_3_lut_rep_47.init = 16'hcaca;
    L6MUX21 i1311 (.D0(n3409), .D1(PC_9__N_159[0]), .SD(n1237), .Z(n3410));
    PFUMX i1652 (.BLUT(n17_adj_437), .ALUT(PC_9__N_169[5]), .C0(n7264), 
          .Z(n3751));
    LUT4 i1_2_lut_3_lut_4_lut_adj_13 (.A(prog[2]), .B(prog[3]), .C(prog[1]), 
         .D(prog[0]), .Z(n4273)) /* synthesis lut_function=(!(A+(B+(C (D)+!C !(D))))) */ ;
    defparam i1_2_lut_3_lut_4_lut_adj_13.init = 16'h0110;
    LUT4 i1_4_lut_adj_14 (.A(n5236), .B(alu_c[0]), .C(ram_out[0]), .D(n3170), 
         .Z(n1622)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))) */ ;
    defparam i1_4_lut_adj_14.init = 16'ha088;
    CCU2D sub_181_add_2_3 (.A0(SP[1]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(SP[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n6631), 
          .COUT(n6632), .S0(n234), .S1(n233));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(186[13:19])
    defparam sub_181_add_2_3.INIT0 = 16'h5555;
    defparam sub_181_add_2_3.INIT1 = 16'h5555;
    defparam sub_181_add_2_3.INJECT1_0 = "NO";
    defparam sub_181_add_2_3.INJECT1_1 = "NO";
    LUT4 i202_2_lut_3_lut (.A(IRQ_EN), .B(key_c), .C(n1242), .Z(n1244)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(78[8:37])
    defparam i202_2_lut_3_lut.init = 16'h2020;
    LUT4 i1_2_lut_adj_15 (.A(n1239), .B(ram_out[0]), .Z(n1609)) /* synthesis lut_function=(A (B)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i1_2_lut_adj_15.init = 16'h8888;
    LUT4 mux_32_Mux_6_i18_3_lut_3_lut (.A(prog[4]), .B(ram_out[6]), .C(D[6]), 
         .Z(n18)) /* synthesis lut_function=(A (C)+!A (B)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam mux_32_Mux_6_i18_3_lut_3_lut.init = 16'he4e4;
    LUT4 mux_649_i8_3_lut_4_lut (.A(n7715), .B(n7706), .C(C[7]), .D(B[7]), 
         .Z(n2304)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam mux_649_i8_3_lut_4_lut.init = 16'hf780;
    PFUMX i1654 (.BLUT(n17), .ALUT(PC_9__N_169[6]), .C0(n7264), .Z(n3753));
    LUT4 i1_2_lut_3_lut_4_lut_adj_16 (.A(IRQ_EN), .B(key_c), .C(n7726), 
         .D(n1242), .Z(n4_adj_455)) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (C+(D))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(78[8:37])
    defparam i1_2_lut_3_lut_4_lut_adj_16.init = 16'hfdf0;
    LUT4 i3405_4_lut (.A(D[7]), .B(n7725), .C(n17_adj_440), .D(prog[1]), 
         .Z(n30)) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(100[5] 230[13])
    defparam i3405_4_lut.init = 16'hc088;
    PFUMX i5357 (.BLUT(n7415), .ALUT(n7414), .C0(prog[2]), .Z(n1854));
    PFUMX mux_730_i3 (.BLUT(n2544), .ALUT(n2556), .C0(n7703), .Z(PC_9__N_159[2]));
    LUT4 i3342_2_lut (.A(ram_out[7]), .B(n5439), .Z(n15)) /* synthesis lut_function=(A (B)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(100[5] 230[13])
    defparam i3342_2_lut.init = 16'h8888;
    LUT4 i1237_3_lut (.A(n3246), .B(n1854), .C(n1237), .Z(n5236)) /* synthesis lut_function=(A (B (C))+!A (B+!(C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i1237_3_lut.init = 16'hc5c5;
    LUT4 i3182_3_lut_4_lut (.A(n7716), .B(prog[4]), .C(PC_temp[2]), .D(n7692), 
         .Z(n2544)) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;
    defparam i3182_3_lut_4_lut.init = 16'hf1e0;
    GSR GSR_INST (.GSR(rst_c));
    LUT4 i1085_2_lut_rep_54_3_lut (.A(IRQ_EN), .B(key_c), .C(n1242), .Z(n7712)) /* synthesis lut_function=(A (B (C))+!A (C)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(78[8:37])
    defparam i1085_2_lut_rep_54_3_lut.init = 16'hd0d0;
    PFUMX mux_730_i2 (.BLUT(n2545), .ALUT(n2557), .C0(n7703), .Z(PC_9__N_159[1]));
    FD1P3AX alu_type_i0_i1 (.D(n7458), .SP(clk_pll_enable_148), .CK(clk_pll), 
            .Q(alu_type[1]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam alu_type_i0_i1.GSR = "DISABLED";
    FD1S3IX statu_FSM_i3 (.D(ram_out[11]), .CK(clk_pll), .CD(n4568), .Q(n1240));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam statu_FSM_i3.GSR = "ENABLED";
    LUT4 i3365_2_lut_2_lut (.A(prog[4]), .B(alu_c[1]), .Z(n2439)) /* synthesis lut_function=(!(A+!(B))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i3365_2_lut_2_lut.init = 16'h4444;
    LUT4 prog_3__bdd_4_lut_5587 (.A(prog[2]), .B(prog[4]), .C(prog[1]), 
         .D(prog[0]), .Z(n7528)) /* synthesis lut_function=(!(A+!(B+!(C+(D))))) */ ;
    defparam prog_3__bdd_4_lut_5587.init = 16'h4445;
    LUT4 n3_bdd_4_lut_4_lut (.A(prog[3]), .B(prog[2]), .C(n7717), .D(n3), 
         .Z(n7457)) /* synthesis lut_function=(!(A+(B (C)+!B !(D)))) */ ;
    defparam n3_bdd_4_lut_4_lut.init = 16'h1504;
    LUT4 i3_4_lut_adj_17 (.A(prog[3]), .B(n7708), .C(n7717), .D(prog[2]), 
         .Z(clk_pll_enable_77)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ;
    defparam i3_4_lut_adj_17.init = 16'h0008;
    LUT4 i207_2_lut_rep_68 (.A(ram_out[11]), .B(n1241), .Z(n7726)) /* synthesis lut_function=(!(A+!(B))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i207_2_lut_rep_68.init = 16'h4444;
    LUT4 mux_32_Mux_4_i18_3_lut_3_lut (.A(prog[4]), .B(ram_out[4]), .C(D[4]), 
         .Z(n18_adj_459)) /* synthesis lut_function=(A (C)+!A (B)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam mux_32_Mux_4_i18_3_lut_3_lut.init = 16'he4e4;
    LUT4 reduce_or_208_i1_2_lut_3_lut (.A(ram_out[11]), .B(n1241), .C(n1240), 
         .Z(n1251)) /* synthesis lut_function=(A (C)+!A (B+(C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam reduce_or_208_i1_2_lut_3_lut.init = 16'hf4f4;
    PFUMX i5550 (.BLUT(n7751), .ALUT(n7752), .C0(prog[2]), .Z(n7753));
    LUT4 i2362_2_lut_rep_69 (.A(prog[0]), .B(prog[1]), .Z(n7727)) /* synthesis lut_function=(!((B)+!A)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam i2362_2_lut_rep_69.init = 16'h2222;
    LUT4 mux_651_i10_3_lut_4_lut (.A(n7713), .B(n7706), .C(D[9]), .D(n2302), 
         .Z(n2316)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;
    defparam mux_651_i10_3_lut_4_lut.init = 16'hf780;
    PFUMX mux_1135_i7 (.BLUT(n2490), .ALUT(n2434), .C0(n7727), .Z(n3210));
    PFUMX i5548 (.BLUT(n7748), .ALUT(n7749), .C0(prog[3]), .Z(n2361));
    LUT4 n3203_bdd_3_lut_5362_3_lut_4_lut (.A(prog[0]), .B(prog[1]), .C(prog[4]), 
         .D(prog[3]), .Z(n7424)) /* synthesis lut_function=(!(A (B (D)+!B ((D)+!C))+!A (D))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam n3203_bdd_3_lut_5362_3_lut_4_lut.init = 16'h00fd;
    PFUMX i5546 (.BLUT(n7745), .ALUT(n7746), .C0(prog[2]), .Z(n7747));
    CCU2D sub_181_add_2_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(SP[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .COUT(n6631), 
          .S1(n235));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(186[13:19])
    defparam sub_181_add_2_1.INIT0 = 16'hF000;
    defparam sub_181_add_2_1.INIT1 = 16'h5555;
    defparam sub_181_add_2_1.INJECT1_0 = "NO";
    defparam sub_181_add_2_1.INJECT1_1 = "NO";
    PFUMX mux_1135_i6 (.BLUT(n2491), .ALUT(n2435), .C0(n7727), .Z(n3209));
    LUT4 i5102_2_lut_3_lut (.A(prog[0]), .B(prog[1]), .C(n2523), .Z(n7196)) /* synthesis lut_function=(A ((C)+!B)+!A (C)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(75[11] 297[5])
    defparam i5102_2_lut_3_lut.init = 16'hf2f2;
    LUT4 i5319_4_lut (.A(prog[1]), .B(n4_adj_448), .C(n7071), .D(n31), 
         .Z(clk_pll_enable_88)) /* synthesis lut_function=(!(A (B+(C))+!A (B+(C+(D))))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i5319_4_lut.init = 16'h0203;
    PFUMX i1648 (.BLUT(n17_adj_446), .ALUT(PC_9__N_169[3]), .C0(n7264), 
          .Z(n3747));
    PFUMX i5544 (.BLUT(n7742), .ALUT(n7743), .C0(prog[2]), .Z(n7744));
    LUT4 i1_2_lut_rep_70 (.A(prog[0]), .B(prog[3]), .Z(n7728)) /* synthesis lut_function=(A (B)) */ ;
    defparam i1_2_lut_rep_70.init = 16'h8888;
    PFUMX i5542 (.BLUT(n7739), .ALUT(n7740), .C0(prog[2]), .Z(n7741));
    LUT4 prog_1__bdd_2_lut_3_lut (.A(prog[0]), .B(prog[3]), .C(prog[1]), 
         .Z(n7663)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ;
    defparam prog_1__bdd_2_lut_3_lut.init = 16'h0808;
    PFUMX i1650 (.BLUT(n17_adj_458), .ALUT(PC_9__N_169[4]), .C0(n7264), 
          .Z(n3749));
    CCU2D add_179_3 (.A0(PC[1]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(PC[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n6626), 
          .COUT(n6627), .S0(PC_9__N_179[1]), .S1(PC_9__N_179[2]));   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(184[18:27])
    defparam add_179_3.INIT0 = 16'h5aaa;
    defparam add_179_3.INIT1 = 16'h5aaa;
    defparam add_179_3.INJECT1_0 = "NO";
    defparam add_179_3.INJECT1_1 = "NO";
    LUT4 i3368_2_lut_2_lut (.A(prog[4]), .B(alu_c[4]), .Z(n2436)) /* synthesis lut_function=(!(A+!(B))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(76[3] 296[11])
    defparam i3368_2_lut_2_lut.init = 16'h4444;
    
endmodule
//
// Verilog Description of module ram
//

module ram (clk_pll, VCC_net, GND_net, ram_we, PC, ram_in, ram_out) /* synthesis NGD_DRC_MASK=1, syn_module_defined=1 */ ;
    input clk_pll;
    input VCC_net;
    input GND_net;
    input ram_we;
    input [9:0]PC;
    input [11:0]ram_in;
    output [11:0]ram_out;
    
    wire clk_pll /* synthesis is_clock=1, SET_AS_NETWORK=clk_pll */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(40[6:13])
    
    DP8KC ram_0_1_0 (.DIA0(ram_in[9]), .DIA1(ram_in[10]), .DIA2(ram_in[11]), 
          .DIA3(GND_net), .DIA4(GND_net), .DIA5(GND_net), .DIA6(GND_net), 
          .DIA7(GND_net), .DIA8(GND_net), .ADA0(VCC_net), .ADA1(GND_net), 
          .ADA2(GND_net), .ADA3(PC[0]), .ADA4(PC[1]), .ADA5(PC[2]), 
          .ADA6(PC[3]), .ADA7(PC[4]), .ADA8(PC[5]), .ADA9(PC[6]), .ADA10(PC[7]), 
          .ADA11(PC[8]), .ADA12(PC[9]), .CEA(VCC_net), .OCEA(VCC_net), 
          .CLKA(clk_pll), .WEA(ram_we), .CSA0(GND_net), .CSA1(GND_net), 
          .CSA2(GND_net), .RSTA(GND_net), .DIB0(GND_net), .DIB1(GND_net), 
          .DIB2(GND_net), .DIB3(GND_net), .DIB4(GND_net), .DIB5(GND_net), 
          .DIB6(GND_net), .DIB7(GND_net), .DIB8(GND_net), .ADB0(GND_net), 
          .ADB1(GND_net), .ADB2(GND_net), .ADB3(GND_net), .ADB4(GND_net), 
          .ADB5(GND_net), .ADB6(GND_net), .ADB7(GND_net), .ADB8(GND_net), 
          .ADB9(GND_net), .ADB10(GND_net), .ADB11(GND_net), .ADB12(GND_net), 
          .CEB(VCC_net), .OCEB(VCC_net), .CLKB(GND_net), .WEB(GND_net), 
          .CSB0(GND_net), .CSB1(GND_net), .CSB2(GND_net), .RSTB(GND_net), 
          .DOA0(ram_out[9]), .DOA1(ram_out[10]), .DOA2(ram_out[11])) /* synthesis MEM_LPC_FILE="ram.lpc", MEM_INIT_FILE="ram.mem", syn_instantiated=1, LSE_LINE_FILE_ID=3, LSE_LCOL=5, LSE_RCOL=2, LSE_LLINE=47, LSE_RLINE=55 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(47[5] 55[2])
    defparam ram_0_1_0.DATA_WIDTH_A = 9;
    defparam ram_0_1_0.DATA_WIDTH_B = 9;
    defparam ram_0_1_0.REGMODE_A = "NOREG";
    defparam ram_0_1_0.REGMODE_B = "NOREG";
    defparam ram_0_1_0.CSDECODE_A = "0b000";
    defparam ram_0_1_0.CSDECODE_B = "0b111";
    defparam ram_0_1_0.WRITEMODE_A = "NORMAL";
    defparam ram_0_1_0.WRITEMODE_B = "NORMAL";
    defparam ram_0_1_0.GSR = "ENABLED";
    defparam ram_0_1_0.RESETMODE = "ASYNC";
    defparam ram_0_1_0.ASYNC_RESET_RELEASE = "SYNC";
    defparam ram_0_1_0.INIT_DATA = "DYNAMIC";
    defparam ram_0_1_0.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000800004040000400004";
    defparam ram_0_1_0.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_1_0.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_1_0.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_1_0.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_1_0.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_1_0.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_1_0.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_1_0.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_1_0.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_1_0.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_1_0.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_1_0.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_1_0.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_1_0.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_1_0.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_1_0.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_1_0.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_1_0.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_1_0.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_1_0.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_1_0.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_1_0.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_1_0.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_1_0.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_1_0.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_1_0.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_1_0.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_1_0.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_1_0.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_1_0.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_1_0.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    DP8KC ram_0_0_1 (.DIA0(ram_in[0]), .DIA1(ram_in[1]), .DIA2(ram_in[2]), 
          .DIA3(ram_in[3]), .DIA4(ram_in[4]), .DIA5(ram_in[5]), .DIA6(ram_in[6]), 
          .DIA7(ram_in[7]), .DIA8(ram_in[8]), .ADA0(VCC_net), .ADA1(GND_net), 
          .ADA2(GND_net), .ADA3(PC[0]), .ADA4(PC[1]), .ADA5(PC[2]), 
          .ADA6(PC[3]), .ADA7(PC[4]), .ADA8(PC[5]), .ADA9(PC[6]), .ADA10(PC[7]), 
          .ADA11(PC[8]), .ADA12(PC[9]), .CEA(VCC_net), .OCEA(VCC_net), 
          .CLKA(clk_pll), .WEA(ram_we), .CSA0(GND_net), .CSA1(GND_net), 
          .CSA2(GND_net), .RSTA(GND_net), .DIB0(GND_net), .DIB1(GND_net), 
          .DIB2(GND_net), .DIB3(GND_net), .DIB4(GND_net), .DIB5(GND_net), 
          .DIB6(GND_net), .DIB7(GND_net), .DIB8(GND_net), .ADB0(GND_net), 
          .ADB1(GND_net), .ADB2(GND_net), .ADB3(GND_net), .ADB4(GND_net), 
          .ADB5(GND_net), .ADB6(GND_net), .ADB7(GND_net), .ADB8(GND_net), 
          .ADB9(GND_net), .ADB10(GND_net), .ADB11(GND_net), .ADB12(GND_net), 
          .CEB(VCC_net), .OCEB(VCC_net), .CLKB(GND_net), .WEB(GND_net), 
          .CSB0(GND_net), .CSB1(GND_net), .CSB2(GND_net), .RSTB(GND_net), 
          .DOA0(ram_out[0]), .DOA1(ram_out[1]), .DOA2(ram_out[2]), .DOA3(ram_out[3]), 
          .DOA4(ram_out[4]), .DOA5(ram_out[5]), .DOA6(ram_out[6]), .DOA7(ram_out[7]), 
          .DOA8(ram_out[8])) /* synthesis MEM_LPC_FILE="ram.lpc", MEM_INIT_FILE="ram.mem", syn_instantiated=1, LSE_LINE_FILE_ID=3, LSE_LCOL=5, LSE_RCOL=2, LSE_LLINE=47, LSE_RLINE=55 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(47[5] 55[2])
    defparam ram_0_0_1.DATA_WIDTH_A = 9;
    defparam ram_0_0_1.DATA_WIDTH_B = 9;
    defparam ram_0_0_1.REGMODE_A = "NOREG";
    defparam ram_0_0_1.REGMODE_B = "NOREG";
    defparam ram_0_0_1.CSDECODE_A = "0b000";
    defparam ram_0_0_1.CSDECODE_B = "0b111";
    defparam ram_0_0_1.WRITEMODE_A = "NORMAL";
    defparam ram_0_0_1.WRITEMODE_B = "NORMAL";
    defparam ram_0_0_1.GSR = "ENABLED";
    defparam ram_0_0_1.RESETMODE = "ASYNC";
    defparam ram_0_0_1.ASYNC_RESET_RELEASE = "SYNC";
    defparam ram_0_0_1.INIT_DATA = "DYNAMIC";
    defparam ram_0_0_1.INITVAL_00 = "0x0000000000000000000000000000000000000000000000000000000000070000C2AA050080000E00";
    defparam ram_0_0_1.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_0_1.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_0_1.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_0_1.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_0_1.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_0_1.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_0_1.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_0_1.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_0_1.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_0_1.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_0_1.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_0_1.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_0_1.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_0_1.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_0_1.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_0_1.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_0_1.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_0_1.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_0_1.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_0_1.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_0_1.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_0_1.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_0_1.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_0_1.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_0_1.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_0_1.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_0_1.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_0_1.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_0_1.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_0_1.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam ram_0_0_1.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    
endmodule
//
// Verilog Description of module ALU
//

module ALU (alu_a, alu_type, alu_b, alu_c, R_11__N_429, GND_net, 
            alu_co, Co_N_435, n7724, alu_cin) /* synthesis syn_module_defined=1 */ ;
    input [11:0]alu_a;
    input [3:0]alu_type;
    input [11:0]alu_b;
    output [11:0]alu_c;
    input R_11__N_429;
    input GND_net;
    output alu_co;
    input Co_N_435;
    input n7724;
    input alu_cin;
    
    wire R_11__N_429 /* synthesis is_clock=1, SET_AS_NETWORK=\ALU_M/R_11__N_429 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(5[20:21])
    
    wire n7779, R_11__N_425, n6643;
    wire [0:0]n3022;
    
    wire R_11__N_421;
    wire [11:0]add_c;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(12[13:18])
    
    wire n7778, R_11__N_417, R_11__N_413, R_11__N_409, R_11__N_405, 
        R_11__N_401, R_11__N_397, R_11__N_393, R_11__N_389, R_11__N_385, 
        R_11__N_372, n7782, n7781, n7785, n7789, n7784, add_co, 
        n6, n7788, n7786, n7783, n7780, n7777, n7774, n7771, 
        n7768, n7787, n7765, n7762, n7759, n7756, n3052, n21, 
        n22, n3338, n3037, n4, n7755, n7754, n7758, n6654, n7757, 
        n6653, n7761, n7760, n7764, n7763, n20, n14, n7767, 
        n6652, n7766, n7770, n6651, n7769, n7775, n7776, n7773, 
        n7772, n6650, n6649, n6648, n6647, n6646, n6645, n6644;
    
    LUT4 mux_968_i1_4_lut_then_4_lut (.A(alu_a[3]), .B(alu_type[2]), .C(alu_b[3]), 
         .D(alu_type[0]), .Z(n7779)) /* synthesis lut_function=(!(A (B+!(C+(D)))+!A (B+!(C (D))))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_968_i1_4_lut_then_4_lut.init = 16'h3220;
    FD1S1A R_11__I_0_i1 (.D(R_11__N_425), .CK(R_11__N_429), .Q(alu_c[0])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=5, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=64 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(28[1] 59[4])
    defparam R_11__I_0_i1.GSR = "DISABLED";
    CCU2D sub_1066_add_2_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(alu_a[0]), .B1(alu_b[0]), .C1(GND_net), 
          .D1(GND_net), .COUT(n6643));
    defparam sub_1066_add_2_1.INIT0 = 16'h0000;
    defparam sub_1066_add_2_1.INIT1 = 16'h5999;
    defparam sub_1066_add_2_1.INJECT1_0 = "NO";
    defparam sub_1066_add_2_1.INJECT1_1 = "NO";
    FD1S1I Co_I_0 (.D(n3022[0]), .CK(Co_N_435), .CD(alu_type[3]), .Q(alu_co)) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=5, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=64 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(28[1] 59[4])
    defparam Co_I_0.GSR = "DISABLED";
    FD1S1A R_11__I_0_i2 (.D(R_11__N_421), .CK(R_11__N_429), .Q(alu_c[1])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=5, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=64 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(28[1] 59[4])
    defparam R_11__I_0_i2.GSR = "DISABLED";
    LUT4 mux_968_i1_4_lut_else_4_lut (.A(add_c[3]), .B(alu_a[3]), .C(alu_type[2]), 
         .D(alu_type[0]), .Z(n7778)) /* synthesis lut_function=(!(A (B (C)+!B (D))+!A (B (C+!(D))+!B ((D)+!C)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_968_i1_4_lut_else_4_lut.init = 16'h0c3a;
    FD1S1A R_11__I_0_i3 (.D(R_11__N_417), .CK(R_11__N_429), .Q(alu_c[2])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=5, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=64 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(28[1] 59[4])
    defparam R_11__I_0_i3.GSR = "DISABLED";
    FD1S1A R_11__I_0_i4 (.D(R_11__N_413), .CK(R_11__N_429), .Q(alu_c[3])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=5, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=64 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(28[1] 59[4])
    defparam R_11__I_0_i4.GSR = "DISABLED";
    FD1S1A R_11__I_0_i5 (.D(R_11__N_409), .CK(R_11__N_429), .Q(alu_c[4])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=5, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=64 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(28[1] 59[4])
    defparam R_11__I_0_i5.GSR = "DISABLED";
    FD1S1A R_11__I_0_i6 (.D(R_11__N_405), .CK(R_11__N_429), .Q(alu_c[5])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=5, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=64 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(28[1] 59[4])
    defparam R_11__I_0_i6.GSR = "DISABLED";
    FD1S1A R_11__I_0_i7 (.D(R_11__N_401), .CK(R_11__N_429), .Q(alu_c[6])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=5, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=64 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(28[1] 59[4])
    defparam R_11__I_0_i7.GSR = "DISABLED";
    FD1S1A R_11__I_0_i8 (.D(R_11__N_397), .CK(R_11__N_429), .Q(alu_c[7])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=5, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=64 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(28[1] 59[4])
    defparam R_11__I_0_i8.GSR = "DISABLED";
    FD1S1A R_11__I_0_i9 (.D(R_11__N_393), .CK(R_11__N_429), .Q(alu_c[8])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=5, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=64 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(28[1] 59[4])
    defparam R_11__I_0_i9.GSR = "DISABLED";
    FD1S1A R_11__I_0_i10 (.D(R_11__N_389), .CK(R_11__N_429), .Q(alu_c[9])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=5, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=64 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(28[1] 59[4])
    defparam R_11__I_0_i10.GSR = "DISABLED";
    FD1S1A R_11__I_0_i11 (.D(R_11__N_385), .CK(R_11__N_429), .Q(alu_c[10])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=5, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=64 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(28[1] 59[4])
    defparam R_11__I_0_i11.GSR = "DISABLED";
    FD1S1A R_11__I_0_i12 (.D(R_11__N_372), .CK(R_11__N_429), .Q(alu_c[11])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=5, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=64 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(28[1] 59[4])
    defparam R_11__I_0_i12.GSR = "DISABLED";
    LUT4 mux_994_i1_4_lut_then_4_lut (.A(alu_a[2]), .B(alu_type[2]), .C(alu_b[2]), 
         .D(alu_type[0]), .Z(n7782)) /* synthesis lut_function=(!(A (B+!(C+(D)))+!A (B+!(C (D))))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_994_i1_4_lut_then_4_lut.init = 16'h3220;
    LUT4 mux_994_i1_4_lut_else_4_lut (.A(add_c[2]), .B(alu_a[2]), .C(alu_type[2]), 
         .D(alu_type[0]), .Z(n7781)) /* synthesis lut_function=(!(A (B (C)+!B (D))+!A (B (C+!(D))+!B ((D)+!C)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_994_i1_4_lut_else_4_lut.init = 16'h0c3a;
    LUT4 mux_1020_i1_4_lut_then_4_lut (.A(alu_a[1]), .B(alu_type[2]), .C(alu_b[1]), 
         .D(alu_type[0]), .Z(n7785)) /* synthesis lut_function=(!(A (B+!(C+(D)))+!A (B+!(C (D))))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_1020_i1_4_lut_then_4_lut.init = 16'h3220;
    LUT4 mux_1048_i1_3_lut (.A(n7789), .B(alu_b[0]), .C(alu_type[3]), 
         .Z(R_11__N_425)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_1048_i1_3_lut.init = 16'hcaca;
    LUT4 mux_1020_i1_4_lut_else_4_lut (.A(add_c[1]), .B(alu_a[1]), .C(alu_type[2]), 
         .D(alu_type[0]), .Z(n7784)) /* synthesis lut_function=(!(A (B (C)+!B (D))+!A (B (C+!(D))+!B ((D)+!C)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_1020_i1_4_lut_else_4_lut.init = 16'h0c3a;
    LUT4 mux_1063_Mux_0_i7_4_lut (.A(add_co), .B(n6), .C(alu_type[2]), 
         .D(n7724), .Z(n3022[0])) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_1063_Mux_0_i7_4_lut.init = 16'hc0ca;
    LUT4 mux_1046_i1_4_lut_then_4_lut (.A(alu_a[0]), .B(alu_type[2]), .C(alu_b[0]), 
         .D(alu_type[0]), .Z(n7788)) /* synthesis lut_function=(!(A (B+!(C+(D)))+!A (B+!(C (D))))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_1046_i1_4_lut_then_4_lut.init = 16'h3220;
    LUT4 mux_1022_i1_3_lut (.A(n7786), .B(alu_b[1]), .C(alu_type[3]), 
         .Z(R_11__N_421)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_1022_i1_3_lut.init = 16'hcaca;
    LUT4 mux_996_i1_3_lut (.A(n7783), .B(alu_b[2]), .C(alu_type[3]), .Z(R_11__N_417)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_996_i1_3_lut.init = 16'hcaca;
    LUT4 mux_970_i1_3_lut (.A(n7780), .B(alu_b[3]), .C(alu_type[3]), .Z(R_11__N_413)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_970_i1_3_lut.init = 16'hcaca;
    LUT4 mux_944_i1_3_lut (.A(n7777), .B(alu_b[4]), .C(alu_type[3]), .Z(R_11__N_409)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_944_i1_3_lut.init = 16'hcaca;
    LUT4 mux_918_i1_3_lut (.A(n7774), .B(alu_b[5]), .C(alu_type[3]), .Z(R_11__N_405)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_918_i1_3_lut.init = 16'hcaca;
    LUT4 mux_892_i1_3_lut (.A(n7771), .B(alu_b[6]), .C(alu_type[3]), .Z(R_11__N_401)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_892_i1_3_lut.init = 16'hcaca;
    LUT4 mux_866_i1_3_lut (.A(n7768), .B(alu_b[7]), .C(alu_type[3]), .Z(R_11__N_397)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_866_i1_3_lut.init = 16'hcaca;
    LUT4 mux_1046_i1_4_lut_else_4_lut (.A(add_c[0]), .B(alu_a[0]), .C(alu_type[2]), 
         .D(alu_type[0]), .Z(n7787)) /* synthesis lut_function=(!(A (B (C)+!B (D))+!A (B (C+!(D))+!B ((D)+!C)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_1046_i1_4_lut_else_4_lut.init = 16'h0c3a;
    LUT4 mux_840_i1_3_lut (.A(n7765), .B(alu_b[8]), .C(alu_type[3]), .Z(R_11__N_393)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_840_i1_3_lut.init = 16'hcaca;
    LUT4 mux_814_i1_3_lut (.A(n7762), .B(alu_b[9]), .C(alu_type[3]), .Z(R_11__N_389)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_814_i1_3_lut.init = 16'hcaca;
    LUT4 mux_788_i1_3_lut (.A(n7759), .B(alu_b[10]), .C(alu_type[3]), 
         .Z(R_11__N_385)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_788_i1_3_lut.init = 16'hcaca;
    LUT4 mux_762_i1_3_lut (.A(n7756), .B(alu_b[11]), .C(alu_type[3]), 
         .Z(R_11__N_372)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_762_i1_3_lut.init = 16'hcaca;
    LUT4 i1240_4_lut (.A(n3052), .B(n21), .C(alu_type[0]), .D(n22), 
         .Z(n3338)) /* synthesis lut_function=(!(A (B+((D)+!C))+!A (B (C)+!B (C (D))))) */ ;
    defparam i1240_4_lut.init = 16'h0535;
    LUT4 i3383_2_lut (.A(n3037), .B(alu_type[0]), .Z(n4)) /* synthesis lut_function=(!(A+!(B))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam i3383_2_lut.init = 16'h4444;
    PFUMX mux_1063_Mux_0_i6 (.BLUT(n4), .ALUT(n3338), .C0(alu_type[1]), 
          .Z(n6));
    LUT4 mux_760_i1_4_lut_then_4_lut (.A(alu_a[11]), .B(alu_type[2]), .C(alu_b[11]), 
         .D(alu_type[0]), .Z(n7755)) /* synthesis lut_function=(!(A (B+!(C+(D)))+!A (B+!(C (D))))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_760_i1_4_lut_then_4_lut.init = 16'h3220;
    LUT4 mux_760_i1_4_lut_else_4_lut (.A(add_c[11]), .B(alu_a[11]), .C(alu_type[2]), 
         .D(alu_type[0]), .Z(n7754)) /* synthesis lut_function=(!(A (B (C)+!B (D))+!A (B (C+!(D))+!B ((D)+!C)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_760_i1_4_lut_else_4_lut.init = 16'h0c3a;
    LUT4 mux_786_i1_4_lut_then_4_lut (.A(alu_a[10]), .B(alu_type[2]), .C(alu_b[10]), 
         .D(alu_type[0]), .Z(n7758)) /* synthesis lut_function=(!(A (B+!(C+(D)))+!A (B+!(C (D))))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_786_i1_4_lut_then_4_lut.init = 16'h3220;
    CCU2D sub_1064_add_2_13 (.A0(alu_b[11]), .B0(alu_a[11]), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n6654), .S1(n3037));
    defparam sub_1064_add_2_13.INIT0 = 16'h5999;
    defparam sub_1064_add_2_13.INIT1 = 16'h0000;
    defparam sub_1064_add_2_13.INJECT1_0 = "NO";
    defparam sub_1064_add_2_13.INJECT1_1 = "NO";
    LUT4 mux_786_i1_4_lut_else_4_lut (.A(add_c[10]), .B(alu_a[10]), .C(alu_type[2]), 
         .D(alu_type[0]), .Z(n7757)) /* synthesis lut_function=(!(A (B (C)+!B (D))+!A (B (C+!(D))+!B ((D)+!C)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_786_i1_4_lut_else_4_lut.init = 16'h0c3a;
    CCU2D sub_1064_add_2_11 (.A0(alu_b[9]), .B0(alu_a[9]), .C0(GND_net), 
          .D0(GND_net), .A1(alu_b[10]), .B1(alu_a[10]), .C1(GND_net), 
          .D1(GND_net), .CIN(n6653), .COUT(n6654));
    defparam sub_1064_add_2_11.INIT0 = 16'h5999;
    defparam sub_1064_add_2_11.INIT1 = 16'h5999;
    defparam sub_1064_add_2_11.INJECT1_0 = "NO";
    defparam sub_1064_add_2_11.INJECT1_1 = "NO";
    LUT4 mux_812_i1_4_lut_then_4_lut (.A(alu_a[9]), .B(alu_type[2]), .C(alu_b[9]), 
         .D(alu_type[0]), .Z(n7761)) /* synthesis lut_function=(!(A (B+!(C+(D)))+!A (B+!(C (D))))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_812_i1_4_lut_then_4_lut.init = 16'h3220;
    LUT4 mux_812_i1_4_lut_else_4_lut (.A(add_c[9]), .B(alu_a[9]), .C(alu_type[2]), 
         .D(alu_type[0]), .Z(n7760)) /* synthesis lut_function=(!(A (B (C)+!B (D))+!A (B (C+!(D))+!B ((D)+!C)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_812_i1_4_lut_else_4_lut.init = 16'h0c3a;
    LUT4 mux_838_i1_4_lut_then_4_lut (.A(alu_a[8]), .B(alu_type[2]), .C(alu_b[8]), 
         .D(alu_type[0]), .Z(n7764)) /* synthesis lut_function=(!(A (B+!(C+(D)))+!A (B+!(C (D))))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_838_i1_4_lut_then_4_lut.init = 16'h3220;
    LUT4 mux_838_i1_4_lut_else_4_lut (.A(add_c[8]), .B(alu_a[8]), .C(alu_type[2]), 
         .D(alu_type[0]), .Z(n7763)) /* synthesis lut_function=(!(A (B (C)+!B (D))+!A (B (C+!(D))+!B ((D)+!C)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_838_i1_4_lut_else_4_lut.init = 16'h0c3a;
    PFUMX i5574 (.BLUT(n7787), .ALUT(n7788), .C0(alu_type[1]), .Z(n7789));
    LUT4 i9_4_lut (.A(alu_a[4]), .B(alu_a[1]), .C(alu_a[7]), .D(alu_a[2]), 
         .Z(n21)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(53[9:15])
    defparam i9_4_lut.init = 16'hfffe;
    LUT4 i10_4_lut (.A(alu_a[10]), .B(n20), .C(n14), .D(alu_a[0]), .Z(n22)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(53[9:15])
    defparam i10_4_lut.init = 16'hfffe;
    PFUMX i5572 (.BLUT(n7784), .ALUT(n7785), .C0(alu_type[1]), .Z(n7786));
    LUT4 i8_4_lut (.A(alu_a[9]), .B(alu_a[6]), .C(alu_a[3]), .D(alu_a[11]), 
         .Z(n20)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(53[9:15])
    defparam i8_4_lut.init = 16'hfffe;
    LUT4 i2_2_lut (.A(alu_a[5]), .B(alu_a[8]), .Z(n14)) /* synthesis lut_function=(A+(B)) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(53[9:15])
    defparam i2_2_lut.init = 16'heeee;
    PFUMX i5570 (.BLUT(n7781), .ALUT(n7782), .C0(alu_type[1]), .Z(n7783));
    LUT4 mux_864_i1_4_lut_then_4_lut (.A(alu_a[7]), .B(alu_type[2]), .C(alu_b[7]), 
         .D(alu_type[0]), .Z(n7767)) /* synthesis lut_function=(!(A (B+!(C+(D)))+!A (B+!(C (D))))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_864_i1_4_lut_then_4_lut.init = 16'h3220;
    CCU2D sub_1064_add_2_9 (.A0(alu_b[7]), .B0(alu_a[7]), .C0(GND_net), 
          .D0(GND_net), .A1(alu_b[8]), .B1(alu_a[8]), .C1(GND_net), 
          .D1(GND_net), .CIN(n6652), .COUT(n6653));
    defparam sub_1064_add_2_9.INIT0 = 16'h5999;
    defparam sub_1064_add_2_9.INIT1 = 16'h5999;
    defparam sub_1064_add_2_9.INJECT1_0 = "NO";
    defparam sub_1064_add_2_9.INJECT1_1 = "NO";
    LUT4 mux_864_i1_4_lut_else_4_lut (.A(add_c[7]), .B(alu_a[7]), .C(alu_type[2]), 
         .D(alu_type[0]), .Z(n7766)) /* synthesis lut_function=(!(A (B (C)+!B (D))+!A (B (C+!(D))+!B ((D)+!C)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_864_i1_4_lut_else_4_lut.init = 16'h0c3a;
    PFUMX i5568 (.BLUT(n7778), .ALUT(n7779), .C0(alu_type[1]), .Z(n7780));
    LUT4 mux_890_i1_4_lut_then_4_lut (.A(alu_a[6]), .B(alu_type[2]), .C(alu_b[6]), 
         .D(alu_type[0]), .Z(n7770)) /* synthesis lut_function=(!(A (B+!(C+(D)))+!A (B+!(C (D))))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_890_i1_4_lut_then_4_lut.init = 16'h3220;
    CCU2D sub_1064_add_2_7 (.A0(alu_b[5]), .B0(alu_a[5]), .C0(GND_net), 
          .D0(GND_net), .A1(alu_b[6]), .B1(alu_a[6]), .C1(GND_net), 
          .D1(GND_net), .CIN(n6651), .COUT(n6652));
    defparam sub_1064_add_2_7.INIT0 = 16'h5999;
    defparam sub_1064_add_2_7.INIT1 = 16'h5999;
    defparam sub_1064_add_2_7.INJECT1_0 = "NO";
    defparam sub_1064_add_2_7.INJECT1_1 = "NO";
    LUT4 mux_890_i1_4_lut_else_4_lut (.A(add_c[6]), .B(alu_a[6]), .C(alu_type[2]), 
         .D(alu_type[0]), .Z(n7769)) /* synthesis lut_function=(!(A (B (C)+!B (D))+!A (B (C+!(D))+!B ((D)+!C)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_890_i1_4_lut_else_4_lut.init = 16'h0c3a;
    PFUMX i5566 (.BLUT(n7775), .ALUT(n7776), .C0(alu_type[1]), .Z(n7777));
    LUT4 mux_916_i1_4_lut_then_4_lut (.A(alu_a[5]), .B(alu_type[2]), .C(alu_b[5]), 
         .D(alu_type[0]), .Z(n7773)) /* synthesis lut_function=(!(A (B+!(C+(D)))+!A (B+!(C (D))))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_916_i1_4_lut_then_4_lut.init = 16'h3220;
    LUT4 mux_916_i1_4_lut_else_4_lut (.A(add_c[5]), .B(alu_a[5]), .C(alu_type[2]), 
         .D(alu_type[0]), .Z(n7772)) /* synthesis lut_function=(!(A (B (C)+!B (D))+!A (B (C+!(D))+!B ((D)+!C)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_916_i1_4_lut_else_4_lut.init = 16'h0c3a;
    LUT4 mux_942_i1_4_lut_then_4_lut (.A(alu_a[4]), .B(alu_type[2]), .C(alu_b[4]), 
         .D(alu_type[0]), .Z(n7776)) /* synthesis lut_function=(!(A (B+!(C+(D)))+!A (B+!(C (D))))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_942_i1_4_lut_then_4_lut.init = 16'h3220;
    CCU2D sub_1064_add_2_5 (.A0(alu_b[3]), .B0(alu_a[3]), .C0(GND_net), 
          .D0(GND_net), .A1(alu_b[4]), .B1(alu_a[4]), .C1(GND_net), 
          .D1(GND_net), .CIN(n6650), .COUT(n6651));
    defparam sub_1064_add_2_5.INIT0 = 16'h5999;
    defparam sub_1064_add_2_5.INIT1 = 16'h5999;
    defparam sub_1064_add_2_5.INJECT1_0 = "NO";
    defparam sub_1064_add_2_5.INJECT1_1 = "NO";
    PFUMX i5564 (.BLUT(n7772), .ALUT(n7773), .C0(alu_type[1]), .Z(n7774));
    LUT4 mux_942_i1_4_lut_else_4_lut (.A(add_c[4]), .B(alu_a[4]), .C(alu_type[2]), 
         .D(alu_type[0]), .Z(n7775)) /* synthesis lut_function=(!(A (B (C)+!B (D))+!A (B (C+!(D))+!B ((D)+!C)))) */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(29[2] 58[10])
    defparam mux_942_i1_4_lut_else_4_lut.init = 16'h0c3a;
    PFUMX i5562 (.BLUT(n7769), .ALUT(n7770), .C0(alu_type[1]), .Z(n7771));
    CCU2D sub_1064_add_2_3 (.A0(alu_b[1]), .B0(alu_a[1]), .C0(GND_net), 
          .D0(GND_net), .A1(alu_b[2]), .B1(alu_a[2]), .C1(GND_net), 
          .D1(GND_net), .CIN(n6649), .COUT(n6650));
    defparam sub_1064_add_2_3.INIT0 = 16'h5999;
    defparam sub_1064_add_2_3.INIT1 = 16'h5999;
    defparam sub_1064_add_2_3.INJECT1_0 = "NO";
    defparam sub_1064_add_2_3.INJECT1_1 = "NO";
    CCU2D sub_1064_add_2_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(alu_b[0]), .B1(alu_a[0]), .C1(GND_net), 
          .D1(GND_net), .COUT(n6649));
    defparam sub_1064_add_2_1.INIT0 = 16'h0000;
    defparam sub_1064_add_2_1.INIT1 = 16'h5999;
    defparam sub_1064_add_2_1.INJECT1_0 = "NO";
    defparam sub_1064_add_2_1.INJECT1_1 = "NO";
    PFUMX i5560 (.BLUT(n7766), .ALUT(n7767), .C0(alu_type[1]), .Z(n7768));
    CCU2D sub_1066_add_2_13 (.A0(alu_a[11]), .B0(alu_b[11]), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n6648), .S1(n3052));
    defparam sub_1066_add_2_13.INIT0 = 16'h5999;
    defparam sub_1066_add_2_13.INIT1 = 16'h0000;
    defparam sub_1066_add_2_13.INJECT1_0 = "NO";
    defparam sub_1066_add_2_13.INJECT1_1 = "NO";
    PFUMX i5558 (.BLUT(n7763), .ALUT(n7764), .C0(alu_type[1]), .Z(n7765));
    CCU2D sub_1066_add_2_11 (.A0(alu_a[9]), .B0(alu_b[9]), .C0(GND_net), 
          .D0(GND_net), .A1(alu_a[10]), .B1(alu_b[10]), .C1(GND_net), 
          .D1(GND_net), .CIN(n6647), .COUT(n6648));
    defparam sub_1066_add_2_11.INIT0 = 16'h5999;
    defparam sub_1066_add_2_11.INIT1 = 16'h5999;
    defparam sub_1066_add_2_11.INJECT1_0 = "NO";
    defparam sub_1066_add_2_11.INJECT1_1 = "NO";
    CCU2D sub_1066_add_2_9 (.A0(alu_a[7]), .B0(alu_b[7]), .C0(GND_net), 
          .D0(GND_net), .A1(alu_a[8]), .B1(alu_b[8]), .C1(GND_net), 
          .D1(GND_net), .CIN(n6646), .COUT(n6647));
    defparam sub_1066_add_2_9.INIT0 = 16'h5999;
    defparam sub_1066_add_2_9.INIT1 = 16'h5999;
    defparam sub_1066_add_2_9.INJECT1_0 = "NO";
    defparam sub_1066_add_2_9.INJECT1_1 = "NO";
    PFUMX i5556 (.BLUT(n7760), .ALUT(n7761), .C0(alu_type[1]), .Z(n7762));
    CCU2D sub_1066_add_2_7 (.A0(alu_a[5]), .B0(alu_b[5]), .C0(GND_net), 
          .D0(GND_net), .A1(alu_a[6]), .B1(alu_b[6]), .C1(GND_net), 
          .D1(GND_net), .CIN(n6645), .COUT(n6646));
    defparam sub_1066_add_2_7.INIT0 = 16'h5999;
    defparam sub_1066_add_2_7.INIT1 = 16'h5999;
    defparam sub_1066_add_2_7.INJECT1_0 = "NO";
    defparam sub_1066_add_2_7.INJECT1_1 = "NO";
    PFUMX i5554 (.BLUT(n7757), .ALUT(n7758), .C0(alu_type[1]), .Z(n7759));
    CCU2D sub_1066_add_2_5 (.A0(alu_a[3]), .B0(alu_b[3]), .C0(GND_net), 
          .D0(GND_net), .A1(alu_a[4]), .B1(alu_b[4]), .C1(GND_net), 
          .D1(GND_net), .CIN(n6644), .COUT(n6645));
    defparam sub_1066_add_2_5.INIT0 = 16'h5999;
    defparam sub_1066_add_2_5.INIT1 = 16'h5999;
    defparam sub_1066_add_2_5.INJECT1_0 = "NO";
    defparam sub_1066_add_2_5.INJECT1_1 = "NO";
    PFUMX i5552 (.BLUT(n7754), .ALUT(n7755), .C0(alu_type[1]), .Z(n7756));
    CCU2D sub_1066_add_2_3 (.A0(alu_a[1]), .B0(alu_b[1]), .C0(GND_net), 
          .D0(GND_net), .A1(alu_a[2]), .B1(alu_b[2]), .C1(GND_net), 
          .D1(GND_net), .CIN(n6643), .COUT(n6644));
    defparam sub_1066_add_2_3.INIT0 = 16'h5999;
    defparam sub_1066_add_2_3.INIT1 = 16'h5999;
    defparam sub_1066_add_2_3.INJECT1_0 = "NO";
    defparam sub_1066_add_2_3.INJECT1_1 = "NO";
    add ADD_M (.alu_a({alu_a}), .alu_b({alu_b}), .alu_cin(alu_cin), .add_c({add_c}), 
        .add_co(add_co), .GND_net(GND_net)) /* synthesis NGD_DRC_MASK=1, syn_module_defined=1 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(16[5] 22[2])
    
endmodule
//
// Verilog Description of module add
//

module add (alu_a, alu_b, alu_cin, add_c, add_co, GND_net) /* synthesis NGD_DRC_MASK=1, syn_module_defined=1 */ ;
    input [11:0]alu_a;
    input [11:0]alu_b;
    input alu_cin;
    output [11:0]add_c;
    output add_co;
    input GND_net;
    
    
    wire precin, co0, co1, co2, co3, co4, co5;
    
    FADD2B addsub_0 (.A0(alu_cin), .A1(alu_a[0]), .B0(alu_cin), .B1(alu_b[0]), 
           .CI(precin), .COUT(co0), .S1(add_c[0])) /* synthesis syn_instantiated=1, LSE_LINE_FILE_ID=4, LSE_LCOL=5, LSE_RCOL=2, LSE_LLINE=16, LSE_RLINE=22 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(16[5] 22[2])
    FADD2B addsub_1 (.A0(alu_a[1]), .A1(alu_a[2]), .B0(alu_b[1]), .B1(alu_b[2]), 
           .CI(co0), .COUT(co1), .S0(add_c[1]), .S1(add_c[2])) /* synthesis syn_instantiated=1, LSE_LINE_FILE_ID=4, LSE_LCOL=5, LSE_RCOL=2, LSE_LLINE=16, LSE_RLINE=22 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(16[5] 22[2])
    FADD2B addsub_2 (.A0(alu_a[3]), .A1(alu_a[4]), .B0(alu_b[3]), .B1(alu_b[4]), 
           .CI(co1), .COUT(co2), .S0(add_c[3]), .S1(add_c[4])) /* synthesis syn_instantiated=1, LSE_LINE_FILE_ID=4, LSE_LCOL=5, LSE_RCOL=2, LSE_LLINE=16, LSE_RLINE=22 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(16[5] 22[2])
    FADD2B addsub_3 (.A0(alu_a[5]), .A1(alu_a[6]), .B0(alu_b[5]), .B1(alu_b[6]), 
           .CI(co2), .COUT(co3), .S0(add_c[5]), .S1(add_c[6])) /* synthesis syn_instantiated=1, LSE_LINE_FILE_ID=4, LSE_LCOL=5, LSE_RCOL=2, LSE_LLINE=16, LSE_RLINE=22 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(16[5] 22[2])
    FADD2B addsub_4 (.A0(alu_a[7]), .A1(alu_a[8]), .B0(alu_b[7]), .B1(alu_b[8]), 
           .CI(co3), .COUT(co4), .S0(add_c[7]), .S1(add_c[8])) /* synthesis syn_instantiated=1, LSE_LINE_FILE_ID=4, LSE_LCOL=5, LSE_RCOL=2, LSE_LLINE=16, LSE_RLINE=22 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(16[5] 22[2])
    FADD2B addsub_5 (.A0(alu_a[9]), .A1(alu_a[10]), .B0(alu_b[9]), .B1(alu_b[10]), 
           .CI(co4), .COUT(co5), .S0(add_c[9]), .S1(add_c[10])) /* synthesis syn_instantiated=1, LSE_LINE_FILE_ID=4, LSE_LCOL=5, LSE_RCOL=2, LSE_LLINE=16, LSE_RLINE=22 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(16[5] 22[2])
    FADD2B addsub_6 (.A0(alu_a[11]), .A1(GND_net), .B0(alu_b[11]), .B1(GND_net), 
           .CI(co5), .S0(add_c[11]), .S1(add_co)) /* synthesis syn_instantiated=1, LSE_LINE_FILE_ID=4, LSE_LCOL=5, LSE_RCOL=2, LSE_LLINE=16, LSE_RLINE=22 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(16[5] 22[2])
    FADD2B precin_inst41 (.A0(GND_net), .A1(GND_net), .B0(GND_net), .B1(GND_net), 
           .CI(GND_net), .COUT(precin)) /* synthesis syn_instantiated=1, LSE_LINE_FILE_ID=4, LSE_LCOL=5, LSE_RCOL=2, LSE_LLINE=16, LSE_RLINE=22 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4_alu.v(16[5] 22[2])
    
endmodule
//
// Verilog Description of module PLL
//

module PLL (clk_c, clk_pll, GND_net) /* synthesis NGD_DRC_MASK=1, syn_module_defined=1 */ ;
    input clk_c;
    output clk_pll;
    input GND_net;
    
    wire clk_c /* synthesis is_clock=1 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(4[9:12])
    wire clk_pll /* synthesis is_clock=1, SET_AS_NETWORK=clk_pll */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(40[6:13])
    
    EHXPLLJ PLLInst_0 (.CLKI(clk_c), .CLKFB(clk_pll), .PHASESEL0(GND_net), 
            .PHASESEL1(GND_net), .PHASEDIR(GND_net), .PHASESTEP(GND_net), 
            .LOADREG(GND_net), .STDBY(GND_net), .PLLWAKESYNC(GND_net), 
            .RST(GND_net), .RESETC(GND_net), .RESETD(GND_net), .RESETM(GND_net), 
            .ENCLKOP(GND_net), .ENCLKOS(GND_net), .ENCLKOS2(GND_net), 
            .ENCLKOS3(GND_net), .PLLCLK(GND_net), .PLLRST(GND_net), .PLLSTB(GND_net), 
            .PLLWE(GND_net), .PLLDATI0(GND_net), .PLLDATI1(GND_net), .PLLDATI2(GND_net), 
            .PLLDATI3(GND_net), .PLLDATI4(GND_net), .PLLDATI5(GND_net), 
            .PLLDATI6(GND_net), .PLLDATI7(GND_net), .PLLADDR0(GND_net), 
            .PLLADDR1(GND_net), .PLLADDR2(GND_net), .PLLADDR3(GND_net), 
            .PLLADDR4(GND_net), .CLKOP(clk_pll)) /* synthesis FREQUENCY_PIN_CLKOP="50.000000", FREQUENCY_PIN_CLKI="50.000000", ICP_CURRENT="9", LPF_RESISTOR="72", syn_instantiated=1, LSE_LINE_FILE_ID=3, LSE_LCOL=5, LSE_RCOL=2, LSE_LLINE=42, LSE_RLINE=45 */ ;   // c:/learning materials/gitee_note/step-fpga/cpu4/cpu4/cpu4.v(42[5] 45[2])
    defparam PLLInst_0.CLKI_DIV = 1;
    defparam PLLInst_0.CLKFB_DIV = 1;
    defparam PLLInst_0.CLKOP_DIV = 10;
    defparam PLLInst_0.CLKOS_DIV = 1;
    defparam PLLInst_0.CLKOS2_DIV = 1;
    defparam PLLInst_0.CLKOS3_DIV = 1;
    defparam PLLInst_0.CLKOP_ENABLE = "ENABLED";
    defparam PLLInst_0.CLKOS_ENABLE = "DISABLED";
    defparam PLLInst_0.CLKOS2_ENABLE = "DISABLED";
    defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED";
    defparam PLLInst_0.VCO_BYPASS_A0 = "DISABLED";
    defparam PLLInst_0.VCO_BYPASS_B0 = "DISABLED";
    defparam PLLInst_0.VCO_BYPASS_C0 = "DISABLED";
    defparam PLLInst_0.VCO_BYPASS_D0 = "DISABLED";
    defparam PLLInst_0.CLKOP_CPHASE = 9;
    defparam PLLInst_0.CLKOS_CPHASE = 0;
    defparam PLLInst_0.CLKOS2_CPHASE = 0;
    defparam PLLInst_0.CLKOS3_CPHASE = 0;
    defparam PLLInst_0.CLKOP_FPHASE = 0;
    defparam PLLInst_0.CLKOS_FPHASE = 0;
    defparam PLLInst_0.CLKOS2_FPHASE = 0;
    defparam PLLInst_0.CLKOS3_FPHASE = 0;
    defparam PLLInst_0.FEEDBK_PATH = "CLKOP";
    defparam PLLInst_0.FRACN_ENABLE = "DISABLED";
    defparam PLLInst_0.FRACN_DIV = 0;
    defparam PLLInst_0.CLKOP_TRIM_POL = "RISING";
    defparam PLLInst_0.CLKOP_TRIM_DELAY = 0;
    defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING";
    defparam PLLInst_0.CLKOS_TRIM_DELAY = 0;
    defparam PLLInst_0.PLL_USE_WB = "DISABLED";
    defparam PLLInst_0.PREDIVIDER_MUXA1 = 0;
    defparam PLLInst_0.PREDIVIDER_MUXB1 = 0;
    defparam PLLInst_0.PREDIVIDER_MUXC1 = 0;
    defparam PLLInst_0.PREDIVIDER_MUXD1 = 0;
    defparam PLLInst_0.OUTDIVIDER_MUXA2 = "DIVA";
    defparam PLLInst_0.OUTDIVIDER_MUXB2 = "DIVB";
    defparam PLLInst_0.OUTDIVIDER_MUXC2 = "DIVC";
    defparam PLLInst_0.OUTDIVIDER_MUXD2 = "DIVD";
    defparam PLLInst_0.PLL_LOCK_MODE = 0;
    defparam PLLInst_0.STDBY_ENABLE = "DISABLED";
    defparam PLLInst_0.DPHASE_SOURCE = "DISABLED";
    defparam PLLInst_0.PLLRST_ENA = "DISABLED";
    defparam PLLInst_0.MRST_ENA = "DISABLED";
    defparam PLLInst_0.DCRST_ENA = "DISABLED";
    defparam PLLInst_0.DDRST_ENA = "DISABLED";
    defparam PLLInst_0.INTFB_WAKE = "DISABLED";
    
endmodule
//
// Verilog Description of module PUR
// module not written out since it is a black-box. 
//

//
// Verilog Description of module TSALL
// module not written out since it is a black-box. 
//

